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PDF LTC4310-2 Data sheet ( Hoja de datos )
| Número de pieza | LTC4310-2 | |
| Descripción | Hot-Swappable I2C Isolators | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
n Bidirectional I2C Communication Between Two
Isolated Buses
n Full Isolation with Inexpensive Ethernet
Transformers or Capacitors
n Low Voltage Level Shifting
n I2C Maximum Operating Frequency:
100kHz for LTC4310-1
400kHz for LTC4310-2
n I2C Specification Compliant VOL, VIL
n ±5kV Human Body Model ESD Protection
n Rise Time Accelerators
n SDA, SCL Hot-Swapping
n Very Low Shutdown Current
n Stuck Bus Disconnect and Recovery
n Thermal Shutdown
n 10-Lead MSOP and 3mm × 3mm DFN Packages
Applications
n Isolated I2C, SMBus and PMBus Interfaces
n Isolated Power Supplies
n Positive-to-Negative Rail Communications
n Power-over-Ethernet
LTC4310-1/LwTwCw.D4ataS3hee1t4U0.co-m2
Hot-Swappable
I2C Isolators
Description
The LTC®4310 provides bidirectional I2C communications
between two I2C buses whose grounds are isolated from
one another. Each LTC4310 encodes I2C bus logic states
into signals that are transmitted across an isolation barrier
to another LTC4310. The receiving LTC4310 decodes the
transmission and drives its l2C bus to the appropriate logic
state. The isolation barrier can be bridged by an inexpensive
Ethernet, or other transformer, to achieve communications
across voltage differences reaching thousands of volts, or
it can be bridged by capacitors for lower voltage isolation.
The LTC4310-1 is intended for use in 100kHz I2C systems.
The LTC4310-2 is intended for 400kHz I2C systems.
Rise time accelerators provide strong pull-up currents on
SCL and SDA rising edges to meet rise time specifications
for heavily loaded systems. Data and clock Hot Swap™
circuitry prevent data corruption when a card is inserted
into or removed from a live bus. When a bus is stuck low
for 37ms, the LTC4310 turns off its pull-down devices and
generates up to sixteen clocks and a STOP bit in an attempt
to free the bus. Driving EN low sets the LTC4310 in a very
low current shutdown mode to conserve power.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
1500V Isolated I2C System
10/100Base-TX
3.3V ETHERNET TRANSFORMER
0.01µF
VCC TXP
RXP VCC
3.3k 3.3k
SDA1
SCL1
LTC4310-1
SDA TXN
SCL RXP
EN
READY
0.01µF
GND RXN
EPF8119S
0.01µF LTC4310-1
RXN SDA
TXP SCL
EN
READY
TXN GND
0.01µF
3.3k
ISOLATED
5V
3.3k
LTC4310 Operating Through
20kV/µs Common Mode Transient
SCL
0V
SDA
2V/DIV
SDA2
SCL2
20kV/µs
0V
2µs/DIV
500V/
DIV
431012 TA01b
431012 TA01a
431012f
1 page  
LTC4310-1/LwTwCw.D4ataS3hee1t4U0.co-m2
Typical Performance Characteristics
ICC vs Temperature, LTC4310-1
5.0 SDA = 0V
SCL = VCC
VCC = 5V
4.8
4.6
VCC = 3.3V
4.4
4.2
4.0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
431012 G01
SDA, SCL Controlled Rising Edge
Rate vs Temperature, LTC4310-1
2.0
VCC = 5V
1.8
1.6
1.4
1.2
–50 –25
VCC = 3.3V
0 25 50 75
TEMPERATURE (°C)
100 125
431012 G02
SDA, SCL Controlled Rising Edge
Rate vs Temperature, LTC4310-2
5.5
5.0 VCC = 5V
4.5
4.0
3.5 VCC = 3.3V
3.0
2.5
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
431012 G03
SDA, SCL Rise Time Accelerator
Pull-Up Current vs Temperature
11
10 VCC = 5V
9
8
7 VCC = 3.3V
6
5
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
431012 G04
SDA, SCL Rise Time Accelerator
Pull-Up Current vs Bus Capacitance
12 TA = 25°C
10
VCC = 5V
8
6
4 VCC = 3.3V
2
0
0 100 200 300 400 500 600 700 800
BUS CAPACITANCE (pF)
431012 G05
SDA,SCL Falling Propagation
Delay vs Temperature
220
200
180 VCC = 3.3V
160
140 VCC = 5V
120
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
431012 G06
431012f
5 Page 
Applications Information
Bus Rising Edge Waveform
When all external pull-downs on SCL1 (Figure 1) turn off,
the SCL1 rising waveform will resemble that shown in
Figure 4. The LTC4310-1 senses that SCL1 is rising and
transmits a message to the other LTC4310-1 to release
SCL2 high. During the transmission, the first LTC4310-1
also drives SCL1 to 0.35V, so that when the transmission
is complete, both buses will rise simultaneously from
0.35V at a rate of (0.35 • VCC)/900ns. This functionality
minimizes the effective skew between the two buses. When
SCL1 reaches 0.35 • VCC, the LTC4310-1 deactivates its
rise rate regulation circuitry. The bus then rises with a
time constant of (RBUS • CBUS) until it reaches 0.45 • VCC,
at which point the IBOOST rise time accelerator pull-up
current is activated.
Figure 5 shows SCL1 and SCL2 for an entire 100kHz
switching cycle. Because the LTC4310-1 regulates the bus
rise rate to (0.35 • VCC)/900ns, the 5V bus signal rises
more quickly than the 3.3V bus signal. Both buses reach
(0.35 • VCC) in approximately 900ns, so the effective skew
between the buses is nearly zero. The LTC4310-2 functions
the same as the LTC4310-1, except the controlled rise rate
is limited to (0.35 • VCC)/300ns.
LTC4310-1/LwTwCw.D4ataS3hee1t4U0.co-m2
Start-Up, Data and Clock Hot Swap Circuitry
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit circuitry until the EN voltage is
high, the device is not in thermal shutdown and the VCC
voltage is above 2.4V. After the LTC4310 exits the POR
state, it activates its transmit circuitry and communicates
its SDA, SCL logic states across the barrier to the other
LTC4310 via its TXP and TXN pins.
The receive circuitry remains deactivated for an additional
900µs after the LTC4310 exits POR. The 900µs filter time is
required for the LTC4310 to charge its RXP and RXN pins
to their DC bias voltage, assuming a 0.01µF common-mode
noise filtering capacitor at the center-tap of the secondary
side of the external transformer. When the filter time has
elapsed, the LTC4310 activates its receive circuitry and
decodes the messages it receives on its RXP and RXN
pins, registering the logic state of the remote I2C bus.
When both the local and remote two-wire buses are “quiet”
(i.e., no data transactions are occurring on either bus), the
LTC4310 then drives its READY pin low to indicate that it
has linked the logic state of the local I2C bus with the logic
state of the remote I2C bus. This means that the LTC4310
will now drive its SDA and SCL pins to the logic state of the
remote I2C bus, as specified by the messages it receives
on RXP and RXN. The LTC4310 considers a two-wire bus
1V/DIV
RISE TIME
ACCELERATOR
ACTIVE
SCL1 SET TO 0.35V
DURING TX
BUS RC
dV/dt
=
0.35 • VCC
900 ns
200ns/DIV
431012 F04
Figure 4. SCL1 Rising Waveform of SCL1
for Application Circuit Shown in Figure 1
1V/DIV
SCL2
SCL1
2µs/DIV
431012 F05
Figure 5. 100kHz SCL Waveforms for
Application Circuit Shown in Figure 1
431012f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC4310-2.PDF ] | |
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