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PDF ADXRS450 Data sheet ( Hoja de datos )
| Número de pieza | ADXRS450 | |
| Descripción | High Performance - Digital Output Gyroscope | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADXRS450 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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Preliminary Technical Data
FEATURES
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
High vibration rejection over a wide frequency range
Excellent 25°/hr null offset stability
Internally temperature compensated
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V and 5V operation
−40°C to +105°C operation
Ultra small, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (Z-axis) response
Innovative ceramic vertical mount package, which can be
oriented for pitch, roll, or yaw response
APPLICATIONS
Rotation sensing medical applications
Rotation sensing industrial and instrumentation
High performance platform stabilization
High Performance,www.DataSheet4U.com
Digital Output Gyroscope
ADXRS450
GENERAL DESCRIPTION
The ADXRS450 is an angular rate sensor (gyroscope) intended
for industrial, medical, instrumentation, stabilization, and other
high performance applications. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS450 to operate in exceedingly harsh environments
where shock and vibration are present.
The ADXRS450 utilizes an internal, continuous self-test archi-
tecture. The integrity of the electromechanical system is checked
by applying a high frequency electrostatic force to the sense
structure to generate a rate signal that can be differentiated from
the baseband rate data and internally analyzed.
The ADXRS450 is capable of sensing angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word, as
part of a 32-bit SPI message.
The ADXRS450 is available in a cavity plastic 16-lead SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across both a wide voltage
range (3.3 V to 5 V) and temperature range (−40°C to +105°C).
CP5
VX
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATION
ADXRS450
Z-AXIS ANGULAR
RATE SENSOR
HV DRIVE
CLOCK
PHASE DIVIDER
LOCKED
LOOP AMPLITUDE
DETECT
BAND-PASS
FILTER
ADC 12
DEMOD
Q DAQ
P DAQ
Q FILTER
ST
CONTROL
ALU
DECIMATION
FILTER
TEMPERATURE
CALIBRATION
FAULT
DETECTION
EEPROM
Figure 1.
LDO
REGULATOR
PDD
DVDD
AVDD
SPI
INTERFACE
MOSI
MISO
SCLK
CS
DVSS
PSS
AVSS
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalog Devicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DVDD 1
RSVD 2
16 SCLK
15 MOSI
RSVD 3
CS 4
MISO 5
ADXRS450
TOP VIEW
(Not to Scale)
14 AVDD
13 DVSS
12 RSVD
PDD 6
PSS 7
VX 8
11 AVSS
10 RSVD
9 CP5
Figure 3. SOIC_CAV Pin Configuration
ADXRS450www.DataSheet4U.com
Table 4. 14-Lead SOIC_CAV Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DVDD
Digital Regulated Voltage. See Figure 21 for the applications circuit diagram.
2
RSVD
Reserved. This pin must be connected to DVSS.
3 NC Reserved. This pin must be connected to DVSS.
4 CS Chip Select.
5
MISO
Master In/Slave Out.
6 PDD Supply Voltage.
7 PSS Switching Regulator Ground.
8 VX High Voltage Switching Node. See Figure 21 for the applications circuit diagram.
9 CP5 High Voltage Supply. See Figure 21 for the applications circuit diagram.
10 NC Reserved. This pin must be connected to DVSS.
11
AVSS
Analog Ground.
12 NC Reserved. This pin must be connected to DVSS.
13
DVSS
Digital Signal Ground.
14
AVDD
Analog Regulated Voltage. See Figure 21 for the applications circuit diagram.
15
MOSI
Master Out/Slave In.
16
SCLK
SPI Clock.
Rev. PrA | Page 5 of 28
5 Page 
Preliminary Technical Data
The transfer function for the Rate Data LPF is given as
⎡1 − Z −64 ⎤2
⎢
⎣
1 − Z −1
⎥
⎦
where:
T= 1 =
1
f0 16 kHz (typ)
ADXRS450www.DataSheet4U.com
The transfer function for the Continuous Self-Test LPF is given as
1
64 − 63Z −1
where:
T = 16 = 1ms (typ)
f0
PRIMARY SIGNAL CHAIN
4ms
GROUP DELAY
<5µs
DELAY
<5µs
DELAY
<5µs
DELAY
ARITHMETIC
LOGIC UNIT
BAND-PASS
FILTER
ADC 12
DEMOD
RATE DATA
LPF
Z-AXIS ANGULAR
RATE SENSOR
CONTINUOUS
SELF-TEST
LPF
<64ms
GROUP DELAY
Figure 23. Primary Signal Chain and Associated Delays
<2.2ms
DELAY
SPI
TRANSACTION
Rev. PrA | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADXRS450.PDF ] | |
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