PDF Am49DL3208G Data sheet ( Hoja de datos )

Número de pieza	Am49DL3208G
Descripción	Stacked Multi-chip Package (MCP) Flash Memory And PSRAM
Fabricantes	Advanced Micro Devices
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No Preview Available ! Am49DL3208G Data Sheet www.DataSheet4U.com September 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 30450 Revision A Amendment +2 Issue Date March 12, 2004 1 page ADVANCE INFORMATION TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash memory Block Diagram . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations. . . . . . . . . . . . . . . . . 9 Table 1. Device Bus Operations .....................................................10 Flash Device Bus Operations . . . . . . . . . . . . . . . 10 Requirements for Reading Array Data ................................... 10 Writing Commands/Command Sequences ............................ 11 Accelerated Program Operation ......................................................11 Autoselect Functions .......................................................................11 Simultaneous Read/Write Operations with Zero Latency ................................................................................... 11 Standby Mode ........................................................................ 11 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12 Table 2. Top Boot Sector Addresses ............................................. 12 Table 3. Top Boot SecSi™ Sector Addresses ............................... 14 Table 4. Bottom Boot Sector Addresses ......................................... 14 Table 5. Bottom Boot SecSi™ Sector Addresses .......................... 15 Sector/Sector Block Protection and Unprotection .................. 16 Table 6. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ............................................................. 16 Table 7. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................... 16 Write Protect (WP#) ................................................................ 17 Temporary Sector Unprotect .................................................. 17 Figure 1. Temporary Sector Unprotect Operation ...........................17 Figure 2. In-System Sector Protect/Unprotect Algorithms .......................................................................................18 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 19 Figure 3. SecSi Sector Protect Verify ..............................................20 Hardware Data Protection ...................................................... 20 Low VCC Write Inhibit .......................................................................20 Write Pulse “Glitch” Protection ........................................................20 Logical Inhibit ..................................................................................20 Power-Up Write Inhibit ....................................................................20 Common Flash Memory Interface (CFI) . . . . . . . 20 Table 8. CFI Query Identification String ..........................................21 Table 9. System Interface String..................................................... 22 Table 10. Device Geometry Definition ............................................22 Table 11. Primary Vendor-Specific Extended Query ......................23 Flash Command Definitions . . . . . . . . . . . . . . . . 24 Reading Array Data ................................................................ 24 Reset Command ..................................................................... 24 Autoselect Command Sequence ............................................ 24 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ............................................................................... 24 Word Program Command Sequence ..................................... 25 Unlock Bypass Command Sequence ..............................................25 Figure 4. Program Operation ..........................................................26 Chip Erase Command Sequence ........................................... 26 Sector Erase Command Sequence ........................................ 26 www.DataSheet4U.com Erase Suspend/Erase Resume Commands ........................... 27 Figure 5. Erase Operation .............................................................. 27 Table 12. Command Definitions ..................................................... 28 Flash Write Operation Status. . . . . . . . . . . . . . . . 29 DQ7: Data# Polling ................................................................. 29 Figure 6. Data# Polling Algorithm .................................................. 29 RY/BY#: Ready/Busy# ............................................................ 30 DQ6: Toggle Bit I .................................................................... 30 Figure 7. Toggle Bit Algorithm ........................................................ 30 DQ2: Toggle Bit II ................................................................... 31 Reading Toggle Bits DQ6/DQ2 ............................................... 31 DQ5: Exceeded Timing Limits ................................................ 31 DQ3: Sector Erase Timer ....................................................... 31 Table 13. Write Operation Status................................................... 32 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 33 Figure 8. Maximum Negative Overshoot Waveform ...................... 33 Figure 9. Maximum Positive Overshoot Waveform ........................ 33 Flash DC Characteristics . . . . . . . . . . . . . . . . . . . 34 CMOS Compatible .................................................................. 34 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 35 Figure 11. Typical ICC1 vs. Frequency ............................................ 35 Pseudo SRAM DC and Operating Characteristics . . . . . . . . . . . . . . . . . . 36 Figure 12. Standby Current ISB CMOS ......................................... 37 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 13. Test Setup .................................................................... 38 Figure 14. Input Waveforms and Measurement Levels ............................................................................................. 38 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 Pseudo SRAM CE#s Timing ................................................... 39 Figure 15. Timing Diagram for Alternating Between Pseudo SRAM and Flash ................................................ 39 Read-Only Operations ........................................................... 40 Figure 16. Read Operation Timings ............................................... 40 Hardware Reset (RESET#) .................................................... 41 Figure 17. Reset Timings ............................................................... 41 Flash Erase and Program Operations .................................... 42 Figure 18. Program Operation Timings .......................................... 43 Figure 19. Accelerated Program Timing Diagram .......................... 43 Figure 20. Chip/Sector Erase Operation Timings .......................... 44 Figure 21. Back-to-back Read/Write Cycle Timings ...................... 45 Figure 22. Data# Polling Timings (During Embedded Algorithms) ..................................................................................... 45 Figure 23. Toggle Bit Timings (During Embedded Algorithms) ..................................................................................... 46 Figure 24. DQ2 vs. DQ6 ................................................................. 46 Temporary Sector Unprotect .................................................. 47 Figure 25. Temporary Sector Unprotect Timing Diagram .......................................................................................... 47 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 48 Alternate CE#f Controlled Erase and Program Operations .............................................................................. 49 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings .............................................. 50 Pseudo SRAM AC Characteristics . . . . . . . . . . . 51 Power Up Time ....................................................................... 51 Read Cycle ............................................................................. 51 Figure 28. Pseudo SRAM Read Cycle—Address March 12, 2004 Am49DL3208G 3 5 Page ADVANCE INFORMATION ORDERING INFORMATION The order number (Valid Combination) is formed by the following: www.DataSheet4U.com Am49DL320 8 G T 71 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT SECTOR T = Top boot B = Bottom boot PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY 8 = 8 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Valid Combinations Order Number Package Marking Am49DL3208GT70I Am49DL3208GB70I T, S M490000032 M490000033 Am49DL3208GT71I Am49DL3208GB71I T, S M490000034 M490000035 MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the result- ing output. The following subsections describe each of these operations in further detail. March 12, 2004 Am49DL3208G 9 11 Page

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