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PDF LH28F320BJHE-PBTLZU Data sheet ( Hoja de datos )
| Número de pieza | LH28F320BJHE-PBTLZU | |
| Descripción | Flash Memory 32Mbit (2Mbitx16/4Mbitx8) | |
| Fabricantes | Sharp Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LH28F320BJHE-PBTLZU (archivo pdf) en la parte inferior de esta página. Total 58 Páginas | ||
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PRELIMINARY PRODUCT SPECIFICATION
Integrated Circwuwiwts.DaGtarSoheuept4U.com
LH28F320BJHE-PBTLZU
Flash Memory
32Mbit (2Mbitx16/4Mbitx8)
(Model Number: LHF32JZU
Lead-free (Pb-free)
Spec. Issue Date: September 14, 2004
Spec No: EL169116
1 page  
LHF32JZU
2
LH28F320BJHE-PBTLZU
32M-BIT ( 2Mbit ×16 / 4Mbit ×8 )
Boot Block Flash MEMORY
www.DataSheet4U.com
■ Low Voltage Operation
VCC=VCCW=2.7V-3.6V Single Voltage
■ OTP(One Time Program) Block
3963 word + 4 word Program only array
■ User-Configurable ×8 or ×16 Operation
■ High-Performance Read Access Time
90ns(VCC=2.7V-3.6V)
■ Operating Temperature
-40°C to +85°C
■ Low Power Management
Typ. 4µA (VCC=3.0V) Standby Current
Automatic Power Savings Mode Decreases ICCR in
Static Mode
Typ. 120µA (VCC=3.0V, TA=+25°C, f=32kHz)
Read Current
■ Optimized Array Blocking Architecture
Two 4K-word (8K-byte) Boot Blocks
Six 4K-word (8K-byte) Parameter Blocks
Sixty-three 32K-word (64K-byte) Main Blocks
Bottom Boot Location
■ Extended Cycling Capability
Minimum 100,000 Block Erase Cycles
■ Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
■ Enhanced Data Protection Features
Absolute Protection with VCCW≤VCCWLK
Block Erase, Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Lockout during Power
Transitions
Block Locking with Command and WP#
Permanent Locking
■ Automated Block Erase, Full Chip Erase,
Word/Byte Write and Lock-Bit Configuration
Command User Interface (CUI)
Status Register (SR)
■ SRAM-Compatible Write Interface
■ Industry-Standard Packaging
48-Lead TSOP
■ ETOXTM* Nonvolatile Flash Technology
■ CMOS Process (P-type silicon substrate)
■ Not designed or rated as radiation hardened
SHARP’s LH28F320BJHE-PBTLZU Flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a
wide range of applications.
LH28F320BJHE-PBTLZU can operate at VCC=2.7V-3.6V and VCCW=2.7V-3.6V or 11.7V-12.3V. Its low voltage operation
capability realize battery life and suits for cellular phone application.
Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component
suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code
+ data storage applications.
For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to
DRAM, the LH28F320BJHE-PBTLZU offers four levels of protection: absolute protection with VCCW≤VCCWLK, selective
hardware block locking or flexible software block locking. These alternatives give designers ultimate control of their code
security needs.
The LH28F320BJHE-PBTLZU is manufactured on SHARP’s 0.25µm ETOXTM* process technology. It come in industry-
standard package: the 48-lead TSOP, ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 1.27
5 Page 
LHF32JZU
8
2 PRINCIPLES OF OPERATION
The LH28F320BJHE-PBTLZU flash memory includes an
on-chip WSM to manage block erase, full chip erase,
word/byte write and lock-bit configuration functions. It
allows for: fixed power supplies during block erase, full
chip erase, word/byte write and lock-bit configuration, and
minimal processor overhead with RAM-like interface
timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the VCCW voltage. High
voltage on VCCW enables successful block erase, full chip
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents−block
erase, full chip erase, word/byte write, lock-bit
configuration, status and identifier codes−are accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any blocwkw. wT.hDiastacSohdeeeti4sU.com
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
2.1 Data Protection
When VCCW≤VCCWLK, memory contents cannot be
altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to VCCW. All write
functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The device’s
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.
Rev. 1.27
11 Page | ||
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