|
|
PDF ARM1156T2-S Data sheet ( Hoja de datos )
| Número de pieza | ARM1156T2-S | |
| Descripción | TCM-only Processor | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ARM1156T2-S (archivo pdf) en la parte inferior de esta página. Total 2 Páginas | ||
|
No Preview Available !
ARM1156T2-S TCM-only Processor
with ECC Protection and Reference Design CW001145
www.DataSheet4U.com
OVERVIEW
The LSI Logic implementation of the ARM1156T2-S processor for cell-based
ASIC provides an integration friendly solution for applications like mass storage
devices that require the deterministic performance of Tightly Coupled Memories
(TCM). This implementation of the ARM1156T2-S processor is a timing-closed
hardmac that runs at 450 MHz and provides a higher-performance option to
the ARM966E-S processor with minimal increase in cost. As a member of the
CoreWare® IP library this core will integrate seamlessly with the ASIC design
flow and will help ensure a right-first-time SOC design. LSI Logic’s ARM1156T2-S
hardmac is already timing closed at 450 MHz, thereby eliminating the effort
and risk of closing processor timing at the ASIC level. The processor supports
the ARMv6T2 architecture, including the new Thumb-2 instruction set which
provides the performance of the ARM instructions with the code compression
of the Thumb instructions. The processor core also conforms to the new
AMBA™ 3.0 AXI bus specification for high-performance systems requiring
high data throughput.
I TCM
with ECC
Debug
Interface
VIC Port
Coprocessor
Controller
TCRAM I/F Core TCRAM I/F
VFP
Memory Protection
Instruction
Interface
Data
Interface
Peripheral
Port
64-bit AXI
64-bit AXI
32-bit AXI
Figure 1. ARM1156T2-S processor block diagram
D TCM
with ECC
FEATURES
• 450 MHz timing-closed hardmac
• LSI Logic G90 0.90 nm 1.0 V
process technology
• Configurable TCMs with 64-bit ECC
• AXI bus interface
• Thumb2 instruction support
• Memory Protection Unit (MPU)
• Reference Design
- SRAM/Flash Controller, AXI to AHB
Bridge, AHB to APB Bridge, ECC
protection and logging, Configurable
AXI Interconnect, SSI/SPI, I2C, Interrupt
Controller, UART, Timers, GPIO
BENEFITS
• 450 MHz performance provides
new high-level of performance for
deterministic applications
• Timing closed hardmac reduces timing
closure risk and turn-around time
• 64-bit ECC on TCMs provides soft
error rate protection required by mass
storage and similar applications
without increasing cost or sacrificing
performance
• Thumb2 instructions provide the
performance of ARM with the density
of Thumb reducing the memory
requirements without sacrificing
performance
• Next generation AXI bus enables
better bus performance
• Reference Design with proven
components provides silicon-proven
jump start on subsystem design
• Expert ARM support to help with
architecture, functionality and
integration
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet ARM1156T2-S.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ARM1156T2-S | TCM-only Processor | LSI Logic |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |