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PDF MAX5874 Data sheet ( Hoja de datos )
| Número de pieza | MAX5874 | |
| Descripción | Dual DAC with LVDS Inputs | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3514; Rev 0; 4/05
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
General Description
The MAX5874 is an advanced 14-bit, 200Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 78dBc spurious-free dynamic range
(SFDR) at fOUT = 16MHz and supports update rates of
200Msps, with a power dissipation of only 260mW.
The MAX5874 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1VP-P to 1VP-P differential
output voltage swing. The device features an integrated
+1.2V bandgap reference and control amplifier to
ensure high-accuracy and low-noise performance. A
separate reference input (REFIO) allows for the use of
an external reference source for optimum flexibility and
improved gain accuracy.
The digital and clock inputs of the MAX5874 accept
3.3V CMOS voltage levels. The device features a flexi-
ble input data bus that allows for dual-port input or a
single-interleaved data port. The MAX5874 is available
in a 68-pin QFN package with an exposed paddle (EP)
and is specified for the extended temperature range
(-40°C to +85°C).
Refer to the MAX5873 and MAX5875 data sheets for
pin-compatible 12-bit and 16-bit versions of the
MAX5874, respectively. Refer to the MAX5877 for an
LVDS-compatible version of the MAX5874.
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination System (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Selector Guide
PART
RESOLUTION UPDATE
(Bits)
RATE (Msps)
MAX5873
12
200
MAX5874
14
200
MAX5875
16
200
MAX5876*
12
250
MAX5877*
14
250
MAX5878
16
250
*Future product—contact factory for availability.
LOGIC
INPUTS
CMOS
CMOS
CMOS
LVDS
LVDS
LVDS
Features
♦ 200Msps Output Update Rate
♦ Noise Spectral Density = -160dBFS/Hz at
fOUT = 16MHz
♦ Excellent SFDR and IMD Performance
SFDR = 78dBc at fOUT = 16MHz (to Nyquist)
SFDR = 74dBc at fOUT = 80MHz (to Nyquist)
IMD = -86dBc at fOUT = 10MHz
IMD = -74dBc at fOUT = 80MHz
♦ ACLR = 75dB at fOUT = 61MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ CMOS-Compatible Digital and Clock Inputs
♦ On-Chip +1.20V Bandgap Reference
♦ Low 260mW Power Dissipation
♦ 68-Lead QFN-EP Package
♦ Evaluation Kit Available (MAX5875EVKIT)
Ordering Information
PART
PIN-
TEMP RANGE PACKAGE
PKG CODE
MAX5874EGK -40°C to +85°C 68 QFN-EP* G6800-4
*EP = Exposed pad.
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A6
A5
A4
A3
A2
A1
A0
N.C.
N.C.
GND
DVDD3.3
GND
GND
AVDD3.3
GND
REFIO
FSADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MAX5874
51 B7
50 B8
49 B9
48 B10
47 B11
46 B12
45 B13
44 SELIQ
43 GND
42 XOR
41 DORI
40 PD
39 TORB
38 CLKP
37 CLKN
36 GND
35 AVCLK
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, external reference VREFIO = +1.25V, output load 50Ω dou-
ble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Analog Supply Current
IAVDD3.3
+ IAVCLK
IAVDD1.8
fDAC = 200Msps, fOUT = 1MHz
Power-down
fDAC = 200Msps, fOUT = 1MHz
Power-down
53
0.001
24
0.001
56
32
mA
mA
Digital Supply Current
IDVDD3.3
IDVDD1.8
fDAC = 200Msps, fOUT = 1MHz
Power-down
fDAC = 200Msps, fOUT = 1MHz
Power-down
1.5
0.5
21
0.001
3
25
mA
mA
Power Dissipation
PDISS
fDAC = 200Msps, fOUT = 1MHz
Power-down
260 300
1.65
mW
Power-Supply Rejection Ratio
PSRR
AVDD3.3 = AVCLK = DVDD3.3 = +3.3V ±5%
(Notes 7, 8)
-0.1
+0.1 %FS/V
Note 2: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design
and characterization data.
Note 3: Nominal full-scale current IOUTFS = 32 x IREF.
Note 4: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5874.
Note 5: Parameter measured single-ended into a 50Ω termination resistor.
Note 6: Not production tested. Guaranteed by design and characterization data.
Note 7: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance.
Note 8: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ω double-terminated,
IOUTFS = 20mA, TA = +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 50Msps)
100
0dBFS
80
-12dBFS
-6dBFS
60
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 100Msps)
100
0dBFS
80
-12dBFS -6dBFS
60
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 150Msps)
100
0dBFS
80
-12dBFS -6dBFS
60
40 40
40
20 20
20
0
0 5 10 15 20 25
fOUT (MHz)
0
0 10 20 30 40 50
fOUT (MHz)
0
0 15 30 45 60 75
fOUT (MHz)
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
+1.2V
REFERENCE
10kΩ
REFIO
1µF
FSADJ
IREF
RSET
DACREF
IREF = VREFIO / RSET
OUTIP
CURRENT-SOURCE
ARRAY DAC
OUTIN
AVDD
CURRENT
SWITCHES
CURRENT
SOURCES
IOUT IOUT
OUTIN OUTIP
Figure 2. Reference Architecture, Internal Reference
Configuration
Table 2. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET
BINARY
TWO’S
COMPLEMENT
OUT+
OUT-
00 0000 0000 0000 10 0000 0000 0000 0
IOUTFS
01 1111 1111 1111 00 0000 0000 0000 IOUTFS / 2 IOUTFS / 2
11 1111 1111 1111 01 1111 1111 1111 IOUTFS
0
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB, DORI)
The TORB input selects between two’s-complement or
binary digital input data. Set TORB to a CMOS-logic-
high level to indicate a two’s-complement input format.
Set TORB to a CMOS-logic-low level to indicate a binary
input format.
The DORI input selects between a dual-port (parallel) or
single-port (interleaved) DAC. Set DORI high to configure
the MAX5874 as a dual-port DAC. Set DORI low to con-
figure the MAX5874 as a single-port DAC. In dual-port
mode, connect SELIQ to ground.
CMOS DAC Inputs (A13/B13–A0/B0, XOR, SELIQ)
The MAX5874 latches input data on the rising edge of
the clock in a user-selectable two’s-complement or
binary format. A logic-high voltage on TORB selects
two’s-complement and a logic-low selects offset
binary format.
The MAX5874 includes a single-ended, CMOS-compati-
ble XOR input. Input data (all bits) are compared with the
Figure 3. Simplified Analog Output Structure
bit applied to XOR through exclusive-OR gates. Pulling
XOR high inverts the input data. Pulling XOR low leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input and
applying decoding to XOR, the digital input data can be
decorrelated from the DAC output, allowing for the trou-
bleshooting of possible spurious or harmonic distortion
degradation due to digital feedthrough on the PC board.
A13/B13–A0/B0, XOR, and SELIQ are latched on the ris-
ing edge of the clock. In single-port mode (DORI pulled
low) a logic-high signal on SELIQ directs the B13–B0
data onto the I-DAC inputs. A logic-low signal at SELIQ
directs data to the Q-DAC inputs. In dual-port (parallel)
mode (DORI pulled high), data on pins A13–A0 are
directed onto the Q-DAC inputs and B13–B0 are directed
onto the I-DAC inputs.
Power-Down Operation (PD)
The MAX5874 also features an active-high power-
down mode that reduces the DAC’s digital current
consumption from 22mA to less than 0.5mA and the
analog current consumption from 77mA to less than
2µA. Set PD high to power down the MAX5874. Set PD
low for normal operation.
When powered down, the power consumption of the
MAX5874 is reduced to less than 1.65mW. The MAX5874
requires 10ms to wake up from power-down and enter a
fully operational state. The PD integrated pulldown resistor
activates the MAX5874 if PD is left floating.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX5874.PDF ] | |
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