PDF IS42R32200C1 Data sheet ( Hoja de datos )

Número de pieza	IS42R32200C1
Descripción	512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
Fabricantes	Integrated Silicon Solution
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IS42R32200C1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM ISSI® www.DataSheet4U.com PRELIMINARY INFORMATION DECEMBER 2005 FEATURES • Clock frequency: 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 2.5V power supply • LVTTL interface • Programmable burst length: (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Industrial temperature availability • Package 400-mil 86-pin TSOP II • Lead free package is available PIN DESCRIPTIONS A0-A10 Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE CS RAS CAS WE Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command Write Enable DQM0 to DQM3 Input/Output Mask OVERVIEW ISSI's 64Mb Synchronous DRAM IS42R32200C1 is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high- speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATION (86-Pin TSOP (Type II) VDD DQ0 VDDQ DQ1 DQ2 GNDQ DQ3 DQ4 VDDQ DQ5 DQ6 GNDQ DQ7 NC VDD DQM0 WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 GNDQ DQ17 DQ18 VDDQ DQ19 DQ20 GNDQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 GND 85 DQ15 84 GNDQ 83 DQ14 82 DQ13 81 VDDQ 80 DQ12 79 DQ11 78 GNDQ 77 DQ10 76 DQ9 75 VDDQ 74 DQ8 73 NC 72 GND 71 DQM1 70 NC 69 NC 68 CLK 67 CKE 66 A9 65 A8 64 A7 63 A6 62 A5 61 A4 60 A3 59 DQM3 58 GND 57 NC 56 DQ31 55 VDDQ 54 DQ30 53 DQ29 52 GNDQ 51 DQ28 50 DQ27 49 VDDQ 48 DQ26 47 DQ25 46 GNDQ 45 DQ24 44 GND VDD GND VDDQ GNDQ NC Power Ground Power Supply for DQ Pin Ground for DQ Pin No Connection Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00B 12/14/05 1 1 page IS42R32200C1 ISSI ® enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation. The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. This com- mand is executed at least 4096 times every 64ms. During an AUTO REFRESH command, address bits are “Don’t Care”. This command corresponds to CBR Auto-refresh. SELF REFRESH During the SELF REFRESH operation, the row address to be refreshed, the bank, and the refresh interval are generated automatically internally. SELF REFRESH can be used to retain data in the SDRAM without external clocking, even if the rest of the system is powered down. The SELF REFRESH operation is started by dropping the CKE pin from HIGH to LOW. During the SELF REFRESH operation all other inputs to the SDRAM become “Don’t Care”.The device must remain in self refresh mode for a minimum period equal to tRAS or may remain in self refresh mode for an indefinite period beyond that.The SELF- REFRESH operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins.The next command cannot be executed until the device internal recovery period (tRC) has elapsed. Once CKE goes HIGH, the NOP command must be issued (minimum of two clocks) to provide time for the completion of any internal refresh in progress. After the self-refresh, since it is impossible to determine the ad- dress of the last row to be refreshed, an AUTO-REFRESH should immediately be performed for all addresses. BURST TERMINATE www.DataSheet4U.com The BURST TERMINATE command forcibly terminates the burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registered READ or WRITE command prior to the BURST TERMINATE. COMMAND INHIBIT COMMAND INHIBIT prevents new commands from being executed. Operations in progress are not affected, apart from whether the CLK signal is enabled NO OPERATION When CS is low, the NOP command prevents unwanted commands from being registered during idle or wait states. LOAD MODE REGISTER During the LOAD MODE REGSITER command the mode register is loaded from A0-A10. This command can only be issued when all banks are idle. ACTIVE COMMAND When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputs on A0-A10 selects the row. Until a PRECHARGE command is issued to the bank, the row remains open for accesses. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00B 12/14/05 5 5 Page IS42R32200C1 ISSI ® FUNCTIONAL DESCRIPTION The 64Mb SDRAMs (512K x 32 x 4 banks) are quad-bank DRAMs which operate at 2.5V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization www.DataSheet4U.com SDRAMs must be powered up and initialized in a predefined manner. The 64M SDRAM is initialized after the power is applied to VDD and VDDQ (simultaneously) and the clock is stable. A 100µs delay is required prior to issuing any command other than a COMMAND INHIBIT or a NOP. The COMMAND INHIBIT or NOP may be applied during the 100µs period and continue should at least through the end of the period. With at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied once the 100µs delay has been satisfied. All banks must be precharged. This will leave all banks in an idle idle state where two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SRDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknown state. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00B 12/14/05 11 11 Page

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