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PDF ICSLV218 Data sheet ( Hoja de datos )
| Número de pieza | ICSLV218 | |
| Descripción | Dual 1-to-8 Low Voltage Clock Buffer/Translator | |
| Fabricantes | Integrated Circuit Systems | |
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PRELIMINARY INFORMATION
ICSLV218
www.DataSheet4U.com
Dual 1-to-8 Low Voltage Clock Buffer/Translator
Description
The ICSLV218 is a high-speed clock buffer consisting
of two independent single-input to eight-output
low-skew, non-inverting clock drivers.
The ICSLV218 has three independent supply rails: The
input supply rail, VDDIN, operates from a fixed 2.5 V
supply, while the output supply rails, VDDA and VDDB,
operate from 2.5 V-3.3 V and 1.8 V-2.5 V supplies
respectively. This configuration, combined with 3.3 V
tolerance on the INA and INB inputs, allows for many
different possibilities of up and/or down voltage
translation.
Features
• Dual 1:8 clock drivers
• Pin-compatible with MK74CB218
• Independent supply rails on input and output banks
for voltage translation
• 3.3 V input tolerance
• Low skew outputs within same bank (150 ps)
• Output Enable tri-states both banks of eight
• Clock speeds up to 200 MHz
• Industrial temperature range (-40 to 85°C)
• 28-pin SSOP (150 mil body) Pb (lead) free package
Block Diagram
VDDA
(2.5V-3.3V)
VDDIN
(2.5V)
VDDB
(1.8V-2.5V)
(3.3V tolerant) INB
QA0
QA1
QA2
QA3
QA4
QA5
QA6
QA7
OE (all outputs) GND
INB (3.3V tolerant)
QB0
QB1
QB2
QB3
QB4
QB5
QB6
QB7
MDS LV218 A
1
Revision 083105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
PRELIMINARY INFORMATION
ICSLV218
Dual 1-to-8 Low Voltage Clock Bwuwffewr./DTaratanSshlaeetot4rU.com
AC Electrical Characteristics
Unless stated otherwise, VDDIN = VDDA = VDDB = 2.5 V ±10%, Ambient Temperature = -40 to 85°C
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Clock Frequency
Propagation Delay, INA to
QA0-QA7
FIN INA or INB, Note 3
CL = 10 pF
0
200 MHz
5 ns
Propagation Delay, INB to
QB0-QB7
CL = 10 pF
5 ns
Output Clock Rise Time
Output Clock Fall Time
Output Duty Cycle
Output to Output Skew
20% to 80%, CL=10 pF
80% to 20%, CL=10 pF
CL=10 pF
Measured on rising
edge at VDD/2, Note 1
45
2.5
2.5
48 55
100 150
ns
ns
%
ps
Output Clock A to B Skew
At VDD/2, Note 2
1500 ps
Output Enable Time
OE high to output on
20 ns
Output Disable Time
OE low to tri-state
20 ns
Notes:
1. Between any two A outputs, or any two B outputs, with equal loading.
2. Between any clock A output and any clock B output with INA connected to INB, and equal loading.
3. Care must be taken not to exceed the absolute maximum junction temperature or power dissipation rating of the
package: Power dissipated = (16 outputs x frequency x VDD2 x CL) < [(Tj - Ta) / θJA].
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Min.
Typ.
100
80
67
60
Max.
Units
°C/W
°C/W
°C/W
°C/W
MDS LV218 A
5
Revision 083105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ICSLV218.PDF ] | |
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