PDF MSP8520 Data sheet ( Hoja de datos )

Número de pieza	MSP8520
Descripción	Multi-Service Security Processor
Fabricantes	PMC-SIERRA
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No Preview Available ! MSP8520 Multi-Service Security Processor www.DataSheet4U.com PRODUCT OVERVIEW PMC-Sierra's MSP8520 Multi-Service Security-enabled processor is designed to meet the needs of IP storage, networking, security appli- ances, and office automation. MSP8520 device integrates standards-based hardware security to accelerate internet protocol security (IPSEC) and secure socket layer (SSL) performance for security appliances, firewalls, networking, IP storage and laser printers/MFPs. The MSP8520 is part of the MSP8500 Series of highly-integrated, feature-rich products that incorporate PMC-Sierra's high performance E9000 microprocessor core. The MSP8520 uses the high-bandwidth Fast Device Bus (FDB) as the system bus to interconnect all the on- chip devices to each other and to the E9000 microprocessor using the Generic Device Interface (GDI). All MSP8500 Series products provide a variety of interfaces including PCI, Ethernet, and ROM, Flash, Compact Flash, SRAM, and other low-speed peripheral interfaces. BLOCK DIAGRAM Security Subsystem DDR1/ DDR2 Controller Local Bus Controller PCI Controller PCI Controller GDI Port GDI Port GDI Port GDI Port GDI Port Fast Device Bus (FDB) GDI Port GDI Port GDI Port GDI Port Central Arbiter Central Interrupt Controller E9000 CPU Core DMA Controller On-chip Memory Channelized DMA Controller Central Processing Interface Packet FIFO GE Port 0 GE Port 1 Gigabit Ethernet (GE) Subsystem Dual UART (DUART) TWI/ MDIO/ MDC Released Product Brief PRODUCT HIGHLIGHTS • Integrated Security subsystem: • Dedicated 4-channel DMA controller for security packet processing • IPSec engine: • Supports all IPSec packet transforms and implements SSL packet transforms • Implements DES/3DES/AES/RC4 crypto and SHA-1/MD-5 hash algorithm support • Random number generator • Public key accelerator • E9000 microprocessor core: • 600 MHz to 1 GHz operation • Dual-issue superscalar 7-stage pipeline • 16 Kbyte L1 Instruction and Data caches with parity and a 256 Kbyte L2 cache with ECC support • 8K entry branch prediction table • Multiple reads with out-of-order return • MMU with 128 total TLB entries, page size range: 4 Kbytes to 256 Mbytes • High-performance Floating Point Unit (IEEE 754) • Fixed-point DSP instructions • 400 MHz Fast Device Bus (FDB) system interconnect: • Multiple master, shared, on-chip bus • Bus performance monitoring • Connects the E9000 CPU and other peripherals to memory and I/O interfaces • 167 – 200 MHz DDR1/DDR2 SDRAM memory controller with a 64-bit data interface: • Supports Class I and Class II SSTL drive strengths • Supports maximum addressing up to 4 Gbytes • Provides DDR2 single-ended DQS signaling so that DDR2 RAMs may be supported and operated in DDR1 mode • DDR1 supports device densities of 64, 128, 256, 512 Mbits and 1 Gbit, DDR2 supports densities of 256, 512 Mbits and 1 Gbit • DDR2 supports device widths of 8 and 16 bits. DDR1 additionally supports 32-bit widths • Supports unbuffered and registered DIMMs PMC-2052101, Issue 2 © Copyright PMC-Sierra, Inc. 2006 All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use. 1 page

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Número de pieza	Descripción	Fabricantes
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