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PDF LP3878-ADJ Data sheet ( Hoja de datos )
| Número de pieza | LP3878-ADJ | |
| Descripción | Micropower 800mA Low Noise(Ceramic Stable) Adjustable Voltage Regulator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2005
LP3878-ADJ
Micropower 800mA Low Noise "Ceramic Stable"
Adjustable Voltage Regulator for 1V to 5V Applications
General Description
The LP3878-ADJ is an 800 mA adjustable output voltage
regulator designed to provide high performance and low
noise in applications requiring output voltages as low as
1.0V.
Using an optimized VIP™ (Vertically Integrated PNP) pro-
cess, the LP3878-ADJ delivers superior performance:
Ground Pin Current: Typically 5.5 mA @ 800 mA load, and
www.DataS1h8e0eµt4AU@.co1m00 µA load.
Low Power Shutdown: The LP3878-ADJ draws less than
10 µA quiescent current when shutdown pin is pulled low.
Precision Output: Guaranteed output voltage accuracy is
1% at room temperature.
Low Noise: Broadband output noise is only 18 µV (typical)
with 10 nF bypass capacitor.
Features
n 1.0V to 5.5V output
n Designed for use with low ESR ceramic capacitors
n Very low output noise
n 8 Lead PSOP and LLP surface mount package
n <10 µA quiescent current in shutdown
n Low ground pin current at all loads
n Over-temperature/over-current protection
n -40˚C to +125˚C operating junction temperature range
Applications
n ASIC Power Supplies In:
- Desktops, Notebooks and Graphic Cards
- Set Top Boxes, Printers and Copiers
n DSP and FPGA Power Supplies
n SMPS Post-Regulator
n Medical Instrumentation
Basic Application Circuit
20120903
*Capacitance values shown are minimum required to assure stability. Larger output capacitor provides improved dynamic response. Output capacitor must
meet ESR requirements (see Application Information).
**The Shutdown pin must be actively terminated (see Application Information). Tie to INPUT (Pin 4) if not used.
VIP™ is a trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation DS201209
www.national.com
1 page  
Typical Performance Characteristics Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL = 1 mA,
CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ = 25˚C.
IGND vs Temperature
Minimum VIN Over Temperature
www.DataSheet4U.com
IGND vs ILoad
20120920
VOUT vs Temperature
20120921
Minimum VIN vs VOUT
20120922
Minimum VIN vs VOUT
20120959
20120951
5
20120952
www.national.com
5 Page 
Application Information (Continued)
It is important to remember that capacitor tolerance and
variation with temperature must be taken into consideration
when selecting an output capacitor so that the minimum
required amount of output capacitance is provided over the
full operating temperature range. (See Capacitor Character-
istics section).
The output capacitor must be located not more than 0.5"
from the output pin and returned to a clean analog ground.
NOISE BYPASS CAPACITOR: The 10 nF capacitor on the
Bypass pin significantly reduces noise on the regulator out-
put and is required for loop stability. However, the capacitor
is connected directly to a high-impedance circuit in the band-
gap reference.
Because this circuit has only a few microamperes flowing in
it, any significant loading on this node will cause a change in
the regulated output voltage. For this reason, DC leakage
current through the noise bypass capacitor must never ex-
www.cDeaetdaS1h0e0entA4U, .acnodmshould be kept as low as possible for best
output voltage accuracy.
The types of capacitors best suited for the noise bypass
capacitor are ceramic and film. High-quality ceramic capaci-
tors with either NPO or COG dielectric typically have very
low leakage. 10 nF polypropolene and polycarbonate film
capacitors are available in small surface-mount packages
and typically have extremely low leakage current.
FEEDFORWARD CAPACITOR
The feedforward capacitor designated CFF in the Basic Ap-
plication circuit is required to increase phase margin and
assure loop stability. Improved phase margin also gives
better transient response to changes in load or input voltage,
and faster settling time on the output voltage when transients
occur. CFF forms both a pole and zero in the loop gain, the
zero providing beneficial phase lead (which increases phase
margin) and the pole adding undesirable phase lag (which
should be minimized). The zero frequency is determined
both by the value of CFF and R1:
fz = 1 / (2 x π x CFF x R1)
The pole frequency resulting from CFF is determined by the
value of CFF and the parallel combination of R1 and R2:
fp = 1 / (2 x π x CFF x (R1 // R2))
At higher output voltages where R1 is much greater than R2,
the value of R2 primarily determines the value of the parallel
combination of R1 // R2. This puts the pole at a much higher
frequency than the zero. As the regulated output voltage is
reduced (and the value of R1 decreases), the parallel effect
of R2 diminishes and the two equations become equal (at
which point the pole and zero cancel out). Because the pole
frequency gets closer to the zero at lower output voltages,
the beneficial effects of CFF are increased if the frequency
range of the zero is shifted slightly higher for applications
with low Vout (because then the pole adds less phase lag at
the loop’s crossover frequency).
CFF should be selected to place the pole zero pair at a
frequency where the net phase lead added to the loop at the
crossover frequency is maximized. The following design
guidelines were obtained from bench testing to optimize
phase margin, transient response, and settling time:
For Vout ≤ 2.5V: CFF should be selected to set the zero
frequency in the range of about 50 kHz to 200 kHz.
For Vout > 2.5V: CFF should be selected to set the zero
frequency in the range of about 20 kHz to 100 kHz.
CAPACITOR CHARACTERISTICS
CERAMIC: The LP3878-ADJ was designed to work with
ceramic capacitors on the output to take advantage of the
benefits they offer: for capacitance values in the 10 µF
range, ceramics are the least expensive and also have the
lowest ESR values (which makes them best for eliminating
high-frequency noise). The ESR of a typical 10 µF ceramic
capacitor is in the range of 5 mΩ to 10 mΩ, which meets the
ESR limits required for stability by the LP3878-ADJ.
One disadvantage of ceramic capacitors is that their capaci-
tance can vary with temperature. Many large value ceramic
capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V
temperature characteristic, which results in the capacitance
dropping by more than 50% as the temperature goes from
25˚C to 85˚C.
Another significant problem with Z5U and Y5V dielectric
devices is that the capacitance drops severely with applied
voltage. A typical Z5U or Y5V capacitor can lose 60% of its
rated capacitance with half of the rated voltage applied to it.
For these reasons, X7R and X5R type ceramic capaci-
tors must be used on the input and output of the
LP3878-ADJ.
SHUTDOWN INPUT OPERATION
The LP3878-ADJ is shut off by pulling the Shutdown input
low, and turned on by pulling it high. If this feature is not to be
used, the Shutdown input should be tied to VIN to keep the
regulator output on at all times.
To assure proper operation, the signal source used to drive
the Shutdown input must be able to swing above and below
the specified turn-on/turn-off voltage thresholds listed in the
Electrical Characteristics section under VON/OFF.
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the
LP3878-ADJ has an inherent diode connected between the
regulator output and input.
During normal operation (where the input voltage is higher
than the output) this diode is reverse-biased.
However, if the output is pulled above the input, this diode
will turn ON and current will flow into the regulator output.
In such cases, a parasitic SCR can latch which will allow a
high current to flow into VIN (and out the ground pin), which
can damage the part.
In any application where the output may be pulled above the
input, an external Schottky diode must be connected from
VIN to VOUT (cathode on VIN, anode on VOUT), to limit the
reverse voltage across the LP3878-ADJ to 0.3V (see Abso-
lute Maximum Ratings).
SETTING THE OUTPUT VOLTAGE
The output voltage is set using resistors R1 and R2 (see
Basic Application Circuit).
The formula for output voltage is:
VOUT = VADJ x (1 + (R1 / R2))
R2 must be less than 5 kΩ to ensure loop stability.
To prevent voltage errors, R1 and R2 must be located near
the LP3878-ADJ and connected via traces with no other
currents flowing in them (Kelvin connect). The bottom of the
R1/R2 divider must be connected directly to the LP3878-
ADJ ground pin.
11 www.national.com
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| PDF Descargar | [ Datasheet LP3878-ADJ.PDF ] | |
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