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PDF ESDALC6V1C2 Data sheet ( Hoja de datos )
| Número de pieza | ESDALC6V1C2 | |
| Descripción | Quad low capacitance TRANSIL array | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ESDALC6V1C2
Quad low capacitance TRANSIL™ array for ESD protection
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
■ Computers
■ Printers
www.Data■SheCeot4mU.mcoumnication systems and cellular phones
■ Video equipment
This device is particularly adapted to the
protection of symmetrical signals
Features
■ 4 unidirectional TRANSIL functions.
■ Breakdown voltage VBR = 6.1 V min.
– Low diode capacitance (12 pF @ 0 V)
– Low leakage current (< 500 nA @ 3 V)
– very small PCB area (1.33 mm2)
■ Coated lead free package
Benefits
■ High ESD protection level
■ High integration
■ Suitable for high density boards
Description
The ESDALC6V1C2 is a monolithic array
designed to protect up to 4 lines againast ESD
transients. The device is ideal for applications
where both reduced line capacitance and board
space saving are required.
TM: TRANSIL is a trademark of STMicroelectronics
Coated lead free Flip-Chip
(5 bumps)
Functional diagram
A1 A3 C1
C3
B2
AB C
1
2
3
Order code
Part number
ESDALC6V1C2
Marking
ED
Complies with the following standards:
IEC 61000-4-2 15 kV (air discharge)
8 kV (contact discharge)
MIL STD 883E - Method 3015-7: class 3
25 kV (Human body model)
August 2006
Rev 1
1/7
www.st.com
1 page  
ESDALC6V1C2
Figure 7. Flip-Chip footprint
Copper pad Diameter :
250µm recommended , 300µm max
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
Ordering information
Figure 8. Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year ww = week)
E
xxz
y ww
Figure 9.
www.DataSheet4U.com
Flip-Chip tape and reel specifications
Dot identifying Pin A1 location
4 ± 0.1
Ø 1.5 ± 0.1
ST E
xxz
yww
ST E
xxz
yww
ST E
xxz
yww
0.73 ± 0.05
4 ± 0.1
All dimensions in mm
User direction of unreeling
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
4 Ordering information
Part number
ESDALC6V1C2
Marking
ED
Package
Flip-Chip
Weight
2.1 mg
Base qty
5000
Delivery mode
Tape and reel
5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ESDALC6V1C2.PDF ] | |
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