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PDF LTC2494 Data sheet ( Hoja de datos )
| Número de pieza | LTC2494 | |
| Descripción | 16-Bit 8-/16-Channel ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Up to 8 Differential or 16 Single-Ended Inputs
■ Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
■ Directly Digitizes High Impedance Sensors with
Full Accuracy
■ 600nV RMS Noise
www■.DaPtraoSghreaemt4Um.caobmle Gain from 1 to 256
■ Integrated High Accuracy Temperature Sensor
■ GND to VCC Input/Reference Common Mode Range
■ Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
■ 2ppm INL, No Missing Codes
■ 1ppm Offset and 15ppm Full-Scale Error
■ 2x Speed Mode/Reduced Power Mode (15Hz Using
Internal Oscillator and 80μA at 7.5Hz Output)
■ No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
■ Single Supply 2.7V to 5.5V Operation
■ Internal Oscillator
■ Tiny 5mm × 7mm QFN Package
APPLICATIONS
■ Direct Sensor Digitizer
■ Direct Temperature Measurement
■ Instrumentation
■ Industrial Process Control
LTC2494
16-Bit 8-/16-Channel ΔΣ ADC
with PGA and Easy Drive
Input Current Cancellation
DESCRIPTION
The LTC®2494 is a 16-channel (8-differential), 16-bit, No
Latency ΔΣ™ ADC with Easy Drive™ technology. The pat-
ented sampling scheme eliminates dynamic input current
errors and the shortcomings of on-chip buffering through
automatic cancellation of differential input current. This
allows large external source impedances, and rail-to-rail
input signals to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2494 includes programmable gain, a high accu-
racy temperature sensor and an integrated oscillator. This
device can be configured to measure an external signal
(from combinations of 16 analog input channels operat-
ing in single ended or differential modes) or its internal
temperature sensor. The integrated temperature sensor
offers 1/2°C resolution and 2°C absolute accuracy. The
LTC2494 can be configured to provide a progammable
gain from 1 to 256 in 8 steps.
The LTC2494 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can be
selected and the first conversion, after a new channel is
selected, is valid.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Data Acquisition System with Temperature Compensation
2.7V TO 5.5V
CH0
CH1
•
•
•
CH7
CH8
•
•
•
CH15
16-CHANNEL
MUX
COM
TEMPERATURE
SENSOR
MUXOUT/
ADCIN
VCC
REF+
IN+
16-BIT ΔΣ ADC
WITH EASY-DRIVE
IN–
REF –
SDI
SCK
SDO
CS
MUXOUT/
ADCIN
FO
OSC
2494 TA01a
0.1μF
10μF
4-WIRE
SPI INTERFACE
Absolute Temperature Error
5
4
3
2
1
0
–1
–2
–3
–4
–5
–55 –30
–5 20 45 70
TEMPERATURE (°C)
95 120
2494 TA01b
2494fb
1
1 page  
LTC2494
DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fEOSC
tHEO
tLEO
tCONV_1
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
tCONV_2
Conversion Time for 2x Speed Mode
www.DataSheet4U.com
fISCK Internal SCK Frequency
DISCK
fESCK
tLESCK
tHESCK
tDOUT_ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 24-Bit Data Output Time
tDOUT_ESCK
t1
t2
t3
t4
tKQMAX
tKQMIN
t5
t7
t8
External SCK 24-Bit Data Output Time
CS↓ to SDO Low
CS↑ to SDO High Z
CS↓ to SCK↑
CS↓ to SCK↑
SCK↓ to SDO Valid
SDO Hold After SCK↓
SCK Set-Up Before CS↓
SDI Setup Before SCK↑
SDI Hold After SCK↑
(Note 16)
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
(Notes 10, 17)
(Notes 10, 11, 15)
(Notes 10, 11, 15)
(Notes 10, 11, 15)
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
(Notes 10, 11, 15)
Internal SCK Mode
External SCK Mode
(Note 5)
(Note 5)
(Note 5)
● 10
4000
● 0.125
50
● 0.125
50
● 157.2
160.3
163.5
● 131
133.6
136.3
● 144.1
146.9
149.9
41036/fEOSC (in kHz)
● 78.7 80.3 81.9
● 65.6 66.9 68.2
● 72.2 73.6 75.1
20556/fEOSC (in kHz)
38.4
fEOSC/8
● 45
55
● 4000
● 125
● 125
● 0.61
●0
0.625
192/fEOSC (in kHz)
24/fESCK (in kHz)
0.64
200
●0
200
●0
200
● 50
● 200
● 15
● 50
● 100
● 100
kHz
μs
μs
ms
ms
ms
ms
ms
ms
ms
ms
kHz
kHz
%
kHz
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREFCM = VREF/2, FS = 0.5VREF/Gain
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output.
2494fb
5
5 Page 
LTC2494
PIN FUNCTIONS
FO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When FO is
connected to GND, the converter uses its internal oscil-
lator running at 307.2kHz. The conversion clock may
also be overridden by driving the FO pin with an external
clock in order to change the output rate and the digital
filter rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
wwwth.DeatSalSeheepetm4Uo.cdoemand remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin . In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
Exposed Pad (Pin 39): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
FUNCTIONAL BLOCK DIAGRAM
TEMP
VCC SENSOR
GND
REF+
REF –
MUXOUTP ADCINP
CH0
CH1
CH15
COM
•
•
•
MUX
–+
DIFFERENTIAL
3RD ORDER
ΔΣ MODULATOR
MUXOUTN ADCINN
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
DECIMATING FIR
ADDRESS
SERIAL
INTERFACE
2494 BD
Figure 1. Functional Block Diagram
FO
(INT/EXT)
SDI
SCK
SDO
CS
2494fb
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2494.PDF ] | |
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