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PDF LP3470IM5-4.63 Data sheet ( Hoja de datos )
| Número de pieza | LP3470IM5-4.63 | |
| Descripción | Tiny Power On Reset Circuit | |
| Fabricantes | National Semiconductor | |
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June 1999
LP3470
Tiny Power On Reset Circuit
General Description
The LP3470 is a micropower CMOS voltage supervisory cir-
cuit designed to monitor power supplies in microprocessor
(µP) and other digital systems. It provides maximum adjust-
ability for power-on-reset (POR) and supervisory functions. It
is available in the following six standard reset threshold volt-
age (VRTH) options: 2.63V, 2.93V, 3.08V, 4.00V, 4.38V, and
4.63V. If other voltage options between 2.4V and 5.0V are
desired please contact your National Semiconductor repre-
sentative.
The LP3470 asserts a reset signal whenever the VCC supply
voltage falls below a reset threshold. The reset time-out pe-
riod is adjustable using an external capacitor. Reset remains
asserted for an interval (programmed by an external capaci-
tor) after VCC has risen above the threshold voltage.
The device is available in the tiny SOT23-5 package.
Key Specifications
n ±1% Reset Threshold Accuracy Over Temperature
n Standard Reset Threshold Voltages: 2.63V, 2.93V,
3.08V, 4.00V, 4.38V, and 4.63V
n Custom Reset Threshold Voltages: For other voltages
between 2.4V and 5.0V contact your National
Semiconductor representative
n Very Low Quiescent Current (16 µA typical)
n Guaranteed Reset valid down to VCC=0.5V
Features
n Tiny SOT23-5 Package
n Open Drain Reset Output
n Programmable Reset Timeout Period Using an External
Capacitor
n Immune to Short VCC Transients
Applications
n Critical µP and µC Power Monitoring
n Intelligent Instruments
n Computers
n Portable/Battery-Powered Equipments
Pin Configuration and Basic Operating Circuit
Pin Configuration
Basic Operating Circuit
DS100016-2
Top View
See NS Package Number
MA05B
DS100016-1
© 1999 National Semiconductor Corporation DS100016
www.national.com
1 page  
Functional Block Diagram
Application Information
Reset Timeout Period
The Reset Timeout Period (tRP) is programmable using an
external capacitor (C1) connected to pin SRT of LP3470. A
Ceramic chip capacitor rated at or above 10V is sufficient.
The Reset Timeout Period (tRP) can be calculated using the
following formula:
tRP (ms) = 2000 x C1 (µF).
For example a C1 of 100 nF will achieve a tRP of 200 ms. If
no delay due to tRP is needed in a certain application, the pin
SRT should be left floating.
Reset Output
In applications like microprocessor (µP) systems, errors
might occur in system operation during power-up,
power-down, or brownout conditions. It is imperative to
monitor the power supply voltage in order to prevent these
errors from occurring.
The LP3470 asserts a reset signal whenever the VCC supply
voltage is below a threshold (VRTH) voltage. Reset is guaran-
teed to be a logic low for VCC > 0.5V. Once VCC exceeds the
reset threshold, the reset is kept asserted for a time period
(tRP) programmed by an external capacitor (C1); after this in-
terval Reset goes to logic high. If a brownout condition oc-
curs (monitored voltage falls below the reset threshold minus
a small hysteresis), Reset goes low. When VCC returns
above the reset threshold, Reset remains low for a time pe-
riod tRP before going to logic high.
DS100016-3
Pull-up Resistor Selection
The LP3470’s Reset output structure is a simple open-drain
N-channel MOSFET switch. A pull-up resistor (R1) should be
connected to VCC.
R1 should be large enough to limit the current through the
output MOSFET (Q1) below 10 mA. A resistor value of more
than 680Ω guarantees this. R1 should also be small enough
to ensure a logic high while supplying all the leakage current
through the Reset pin. A resistor value of less than 68kΩ sat-
isfies this condition. A typical pull-up resistor value of 20 kΩ
is sufficient in most applications.
Negative-Going VCC Transients
The LP3470 is relatively immune to short duration
negative-going VCC transients (glitches). The Typical Oper-
ating Characteristics show the Maximum Transient Duration
vs. Negative Transient Amplitude (graph titled Transient Re-
jection), for which reset pulses are not generated. This graph
shows the maximum pulse width a negative-going VCC tran-
sient may typically have without causing a reset pulse to be
issued. As the transient amplitude increases (i.e. goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. A 0.1 µF bypass capacitor mounted
close to VCC provides additional transient immunity.
5 www.national.com
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