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PDF IS65LV256AL Data sheet ( Hoja de datos )

Número de pieza IS65LV256AL
Descripción 32K x 8 LOW VOLTAGE CMOS STATIC RAM
Fabricantes Integrated Silicon Solution 
Logotipo Integrated Silicon Solution Logotipo



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IS65LV256AL
IS62LV256AL
ISSI®
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
MARCH 2006
FEATURES
• High-speed access time: 20, 45 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 17 µW (typical) CMOS standby
— 50 mW (typical) operating
www.DataTSTheLect4oUm.cpomatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Industrial and Automotive temperatures avail-
able
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62/65LV256AL is a very high-speed, low
power, 32,768-word by 8-bit static RAM. It is fabricated
using ISSI's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields access times as fast as 15 ns
maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65LV256AL is available in the JEDEC standard
28-pin SOJ, 28-pin SOP, and the 28-pin 450-mil TSOP
package.
A0-A14
VDD
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
32K x 8
MEMORY ARRAY
COLUMN I/O
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
1

1 page




IS65LV256AL pdf
IS65LV256AL
IS62LV256AL
ISSI®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
tRC Read Cycle Time
tAA Address Access Time
tOHA Output Hold Time
tACE CE Access Time
tDOE OE Access Time
tLZOE(2)
OE to Low-Z Output
tHZOE(2)
OE to High-Z Output
www.DatatLSZChEe(2e) t4U.comCE to Low-Z Output
tHZCE(2)
CE to High-Z Output
tPU(3) CE to Power-Up
tPD(3) CE to Power-Down
-20 ns
Min. Max.
20 —
— 20
2—
— 20
— 10
0—
9
3—
9
0—
— 18
-45 ns
Min. Max.
45 —
— 45
2—
— 45
— 25
0—
0 20
3—
0 20
0—
— 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3.3V
635 Ω
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
702 Ω
3.3V
635 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
702 Ω
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
5

5 Page





IS65LV256AL arduino
PACKAGING INFORMATION
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
ISSI ®
www.DataSheet4U.com
EH
N
D
S
SEATING PLANE
A
L
e B A1
αC
Plastic TSOP (T—Type I)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
No. Leads
28
A 1.00 1.20
0.037 0.047
A1 0.05 0.20
B 0.16 0.27
0.002 0.008
0.006 0.011
C 0.10 0.20
0.004 0.008
D 7.90 8.10
E 11.70 11.90
0.308 0.316
0.456 0.465
H 13.20 13.60
0.515 0.531
e 0.55 BSC
L 0.30 0.70
0.022 BSC
0.011 0.027
α 0° 5°
0° 5°
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
Integrated Silicon Solution, Inc.
PK13197T28 Rev. B 01/31/97

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