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PDF CY25701 Data sheet ( Hoja de datos )
| Número de pieza | CY25701 | |
| Descripción | Programmable High Frequency Crystal Oscillator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY25701 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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CY25701
Programmable High Frequency Crystal
Oscillator with Spread Spectrum (SSXO)
and No Spread Spectrum (XO) Option
Features
■ Crystal Oscillator with Spread Spectrum Clock (SSXO)
■ No Spread Spectrum (XO) Option
■ Wide operating output clock frequency range of 10 –166 MHz
■ Programmable spread spectrum with nominal 31.5 kHz
modulation frequency
■ Center spread: ±0.25% to ±2.0%
www■.DDaotwanShseperte4aUd.c: o–m0.5% to –4.0%
■ No spread: ± 0.0%
■ Integrated phase-locked loop (PLL)
■ 85 ps typical cycle-to-cycle jitter with SSCLK = 133 MHz
■ 3.3V operation
■ Output enable function
■ Package available in 4-Pin ceramic LCC SMD
■ Pb-free package
■ Industrial temperature from –40°C to 85°C
Benefits
■ Provides a wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction to meet
regulatory agency electromagnetic compliance (EMC) require-
ments. Reduces development and manufacturing costs and
time-to-market.
■ This versatile programming feature enables the user to switch
between SSXO (with Spread) and XO (without Spread)
functions with ease.
■ Internal PLL to generate up to 166 MHz output.
■ Suitable for most PC, consumer, and networking applications
■ Application compatibility in standard and low-power systems
■ In house programming of samples and prototype quantities is
available using CY3672 programming kit and CY3724 socket
adapters. Production quantities are available through Cypress’
value added distribution partners or by using third party
programmers from BP Microsystems, and HiLo Systems, and
others.
Logic Block Diagram
RFB
CXIN
CXOUT
1
OE
PLL
with
MODULATION
CONTROL
PROGRAMMABLE
CONFIGURATION
4
VDD
2
VSS
OUTPUT
DIVIDERS
and
MUX
3
SSCLK
Pin Configuration
CY25701
4-pin Ceramic SMD
4
VDD
3
SSCLK
OE VSS
12
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07313 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 24, 2007
1 page  
Switching Waveforms
Figure 2. Duty Cycle Waveform
Cycle Timing (DC = t1A/t1B)
SSCLK
t1A
t1B
CY25701
Figure 3. Output Rise/Fall Time Waveform
www.DataSheet4U.com
SSCLK
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 4. Output Enable/Disable Timing Waveforms
OUTPUT
ENABLE
VDD
0V
VIH
VIL TOE2
SSCLK
(Asynchronous)
High Impedance
TOE1
Document Number: 001-07313 Rev. *B
Page 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY25701.PDF ] | |
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