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PDF HMD4M32M8G Data sheet ( Hoja de datos )
| Número de pieza | HMD4M32M8G | |
| Descripción | 16Mbyte(4Mx32) Fast Page Mode | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD4M32M8G
16Mbyte(4Mx32) Fast Page Mode, 2K/4K Refresh 72Pin SIMM
Part No. HMD4M32M8G, HMD4M32M8AG
GENERAL DESCRIPTION
The HMD4M32M8G is a 4M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD4M32M8G- -2,048 Cycles/32ms Ref . Gold
HMD4M32M8AG- 4,096 Cycles/64ms Ref . Gold
w Access times : 50, 60ns
w High-density 16MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w FP(Fast Page) mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
MARKING
-5
-6
M
PERFORMANCE RANGE
Speed tRAC
tCAC
tRC
5
50ns
13ns
90ns
6
60ns
15ns
110ns
PRESENCE DETECT PINS
Pin
PD1
PD2
PD3
PD4
50ns
Vss
NC
Vss
Vss
URL: www.hbe.co.kr
REV. 1.0(August. 2002)
60ns
Vss
NC
NC
NC
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 25 DQ22 49 DQ8
2
DQ0
26
DQ7
50 DQ24
3 DQ16 27 DQ23 51
DQ9
4
DQ1
28
A7
52 DQ25
5 DQ17 29 A11 53 DQ10
6
DQ2
30
Vcc
54 DQ26
7 DQ18 31 A8 55 DQ11
8
DQ3
32
A9
56 DQ27
9 DQ19 33 NC 57 DQ12
10 Vcc 34 /RAS2 58 DQ28
11 NC 35 NC 59 Vcc
12 A0 36 NC 60 DQ29
13 A1 37 NC 61 DQ13
14 A2 38 NC 62 DQ30
15 A3 39 Vss 63 DQ14
16 A4 40 /CAS0 64 DQ31
17 A5 41 /CAS2 65 DQ15
18 A6 42 /CAS3 66 NC
19 A10 43 /CAS1 67
Vss
20 DQ4 44 /RAS0 68
PD2
21 DQ20 45 NC 69 PD3
22 DQ5 46 NC 70 PD4
23 DQ21 47
/WE
71
NC
24 DQ6 48 NC 72 Vss
A0 – A11 : Address Input(4K Ref.)
A0 – A10 : Address Input(2K Ref.)
*Note : A11 is used for only HMD4M32M8AG
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD4M32M8G
Column address hold referenced to /RAS
tAR 40 45 ns
Column Address to /RAS lead time
tRAL 25 30 ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
40
45
ns
Write command pulse width
tWP 10 10 ns
Write command to /RAS lead time
tRWL
15
15
ns
Write command to /CAS lead time
www.DataSheDeat4taU-.icnosmet-up time
tCWL
13
15
ns
tDS 0 0 ns
Data-in hold time
tDH 10 15 ns
Data-in hold referenced to /RAS
tDHR
40
45
ns
Refresh period 2K Ref.
tREF 32 32 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA 30 35 ns
Fast page mode cycle time
tPC 35 40 ns
/CAS precharge time (Fast page)
tCP 10 10 ns
/RAS pulse width (Fast page )
tRASP
50 200K 60 200K ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
/CAS precharge(C-B-R counter test)
NOTES
tCPT 20 20 ns
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
URL: www.hbe.co.kr
REV. 1.0(August. 2002)
5 HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HMD4M32M8G.PDF ] | |
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