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PDF HT82V26A Data sheet ( Hoja de datos )
| Número de pieza | HT82V26A | |
| Descripción | 16-Bit CCD/CIS Analog Signal Processor | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82V26A
16-Bit CCD/CIS Analog Signal Processor
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 5V (Typ.)
· Low power consumption at 400mW (Typ.)
· Power-down mode: Under 2mA (Typ.)
· 16-bit 30 MSPS A/D converter
· Guaranteed won¢t miss codes
www.DataSheet4U·.co1m~6 programmable gain
· Correlated Double Sampling
· ±250mV programmable offset
· Input clamp circuitry
Applications
Flatbed document scanners
Film scanners
· Internal voltage reference
· Multiplexed byte-wide output (8+8 format)
· Programmable 3-wire serial interface
· 3V/5V digital I/O compatibility
· 3-channel operation up to 30 MSPS
· 2-channel (Even-Odd) operation up to 30 MSPS
· 1-channel operation up to 25 MSPS
· 28-pin SSOP/SOP package (lead-free on request)
Digital color copiers
Multifunction peripherals
General Description
The HT82V26A is a complete analog signal processor
for CCD imaging applications. It features a 3-channel
architecture designed to sample and condition the out-
puts of tri-linear color CCD arrays. Each channel con-
sists of an input clamp, Correlated Double Sampler
(CDS), offset DAC and Programmable Gain Amplifier
(PGA), and a high performance 16-bit A/D converter.
The CDS amplifiers may be disabled for use with sen-
sors such as Contact Image Sensors (CIS) and CMOS
active pixel sensors, which do not require CDS.
The 16-bit digital output is multiplexed into an 8-bit out-
put word that is accessed using two read cycles. The in-
ternal registers are programmed through a 3-wire serial
interface, which provides gain, offset and operating
mode adjustments.
The HT82V26A operates from a single 5V power supply,
typically consumes 400mW of power.
Rev. 1.00
1 August 16, 2005
1 page  
Timing Specification
Symbol
Parameter
Clock Parameters
tPRA 3-channel pixel rate
tPRB 2-channel (Even-Odd) pixel rate
tPRC 1-channel pixel rate
tADCLK
ADCCLK Pulse Width
tC1 CDSCLK1 Pulse Width
tC2 CDSCLK2 Pulse Width
tC1C2
CDSCLK1 Falling to CDSCLK2 Rising
tADC1
ADCCLK Rising to CDSCLK1 Falling
tADC2
ADCCLK Rising to CDSCLK2 Falling
tAD Analog Sampling Delay
3-Channel Mode Only
www.DataSheet4U.ctaoCm2C1
CDSCLK2 Falling to CDSCLK1 Rising
taC2ADR
CDSCLK2 Falling to ADCCLK Rising
2-Channel Mode Only
tbC2ADR
CDSCLK2 Falling to ADCCLK Rising
tbC1ADR
CDSCLK1 Rising to ADCCLK Rising
tbC2C1
CDSCLK2 Falling to CDSCLK1 Rising
1-Channel Mode Only
tcC2C1
CDSCLK2 Falling to CDSCLK1 Rising
tcC1ADF
CDSCLK1 Rising to ADCCLK Falling
tcC2ADR
CDSCLK2 Falling to CDSCLK1 Rising
Serial Interface
fSCLK
Maximum SCLK Frequency
tLS SLOAD to SCLK Setup Time
tLH SCLK to SLOAD Hold Time
tDS SDATA to SCLK Rising Setup Time
tDH SCLK Rising to SDATA Hold Time
tRDV Falling to SDATA Valid
Data Output
tOD Output Delay
Latency (Pipeline Delay)
Min.
100
66
40
16
12
12
0
0
0
5
30
30
30
15
15
15
0
20
10
10
10
10
10
10
¾
¾
Typ.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
8
9
HT82V26A
Max.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
Cycles
Rev. 1.00
5 August 16, 2005
5 Page 
HT82V26A
A n a lo g In p u t
(G , B )
C D S C LK 2
A D C C LK
O u tp u t D a ta
D 7~D 0
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P ix e l ( N + 3 )
tC 2 tb C 2 A D R
P ix e l ( N + 4 )
tA D
P ix e l ( N + 5 )
P ix e l ( N + 6 )
tb P R B
tA D C L K
tA D C 2
tA D C 2
tb C 2 A D R
tA D C L K
tO D
B (N -4 ) B (N -4 ) G (N -3 ) G (N -3 ) B (N -3 ) B (N -3 ) G (N -2 ) G (N -2 ) B (N -2 ) B (N -2 ) G (N -1 ) G (N -1 ) B (N -1 ) B (N -1 )
H ig h L o w H ig h L o w H ig h L o w H ig h L o w H ig h L o w H ig h L o w H ig h L o w
B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te
G (N )
H ig h
B y te
2-Channel SHA Mode Timing (Select G-B Mode)
A n a lo g In p u t
P ix e l
(N + 5 )
tA D
P ix e l
(N + 6 )
P ix e l
(N + 7 )
tC 2
P ix e l
(N + 8 )
P ix e l
(N + 9 )
P ix e l
(N + 1 0 )
tP R C
P ix e l
(N + 1 1 )
C D S C LK 2
tC C 2 A D F
tA D C 2
tA D C 2
tC C 2 A D F
tA D C L K
tA D C L K
A D C C LK
O u tp u t D a ta
D 7~D 0
P ix e l
(N -7 )
P ix e l
(N -6 )
H ig h
B y te
P ix e l
(N -6 )
Low
B y te
P ix e l
(N -5 )
H ig h
B y te
P ix e l
(N -5 )
Low
B y te
P ix e l
(N -4 )
H ig h
B y te
P ix e l
(N -4 )
Low
B y te
P ix e l
(N -3 )
H ig h
B y te
P ix e l
(N -3 )
Low
B y te
P ix e l
(N -2 )
H ig h
B y te
P ix e l
(N -2 )
Low
B y te
P ix e l
(N -1 )
H ig h
B y te
P ix e l
(N -1 )
Low
B y te
tO D
P ix e l
(N )
H ig h
B y te
P ix e l
(N )
Low
B y te
P ix e l
(N + 1 )
H ig h
B y te
1-Channel SHA Mode Timing
Rev. 1.00
11 August 16, 2005
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HT82V26A.PDF ] | |
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