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PDF CY22701 Data sheet ( Hoja de datos )
| Número de pieza | CY22701 | |
| Descripción | 1 PLL In-System Programmable Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY22701
1 PLL In-System Programmable Clock Generator
Features
• In-system programmable through I2C Serial
Programming Interface (SPI)
• Programmable SRAM and non-volatile EEPROM
memory bits with 3.3V supply
• Integrated, phase-locked loop with programmable P
and Q counters, output dividers
• Low-jitter, high-accuracy outputs
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• 8-lead SOIC
Benefits
• Custom timing solutions for designs not suitable for
factory custom silicon, Xtals, or ASICs for production
• Program and optimize designs while chip is on system
board
• Programming voltages contained in chip
• High-performance PLL enables control of output
frequencies that are customizable to support a wide
range of applications
• Meets critical timing requirements in complex system
designs
• Meets industry-standard voltage platforms
• Industry standard packaging saves on board space
Part Number
CY22701
No. of Outputs
Input Frequency Range
Output Frequency Range
2 1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial}
80 kHz –167 MHz (3.3V) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.}
Logic Block Diagram
XIN
XOUT
[I2C- SPI:]
WP
SCL
SDAT
OSC
QΦ
VCO
P
PLL
Clock
Configuration
EEPROM
Memory Array
VDD VSS
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
CLK1
CLK2
Pin Configuration
XIN 1
VDD 2
SDA 3
VSS 4
8 XOUT
7 CLK2/WP
6 CLK1
5 SCL
8 PIN SOIC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07698 Rev. *B
Revised February 8, 2005
1 page  
PRELIMINARY
CY22701
DCXO
PLL Frequency, Q Counter
The default clock configuration of the CY22701 has 256 stored
values that are used to adjust the frequency of the crystal oscil-
lator, by changing the load capacitance. In order to use these
stored values, the clock configuration must be reprogrammed
to enable the DCXO feature.
To Configure for DCXO Operation
• XCapSrc, Register 12H[5] = 0
• XDRV[1:0], Register 12H[4:3] = (see Table 2)
Once the clock configuration block is programmed for DCXO
operation, the SPI may be used to dynamically change the
capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency. Thus, the crystal oscillator frequency can be
www.DaadtajuSshteeedt4frUo.cmom–150 ppm of the nominal frequency value to
+150 ppm of the nominal frequency value. “Nominal frequency
– 150 ppm” is achieved by writing 00000000 into the CapLoad
register, and “nominal frequency + 150 ppm” is achieved by
writing 11111111 into the CapLoad register
Write Protect (WP) Registers
To reconfigure pin 7 as WP, to control enable/disable of write
protection, use the SPI to write the following:
WPSrc, Register 11H[3] = 0
CLK2, Register 09H[4] = 0
CLKSRC 2,1,0, Register 45H[3:1] = 111
When active (WP = 1), WP prevents the control logic for the
EE from initiating a erase/program cycle for the EEPROM
blocks. All serial shifting works as normal.
To reconfigure pin 7 as CLK2, use the SPI to write the
following:
WPSrc, Register 11H[3] = 1
CLK2, Register 09H[4] = 1
CLKSRC 2,1,0, Registers 45H[3:1] = see Table 11
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7-bit variable with
a maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Qtotal.
Qtotal is defined by the formula:
Qtotal = Q + 2.
The minimum value of Qtotal is 2. The maximum value of Qtotal
is 129. Register 42H is defined in Table 6.
Stable operation of the CY22701 cannot be guaranteed if
REF/Qtotal falls below 250 kHz. Qtotal bit locations and values
are defined in Table 6.
PLL Frequency, P Counter
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Qtotal) value to achieve the
VCO frequency. The product counter, defined as Ptotal, is
made up of two internal variables, PB and PO. The formula for
calculating Ptotal is:
Ptotal = (2(PB + 4) + PO)
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see section, Charge Pump Settings
[40H(2..0)] on page 6”). The 3 MSBs of register 40H are preset
and reserved and cannot be changed.
PO is a single bit variable, defined in register 42H(7). This
allows for odd numbers in Ptotal.
The remaining 7 bits of 42H are used to define the Q counter,
as shown in Table 6.
The minimum value of Ptotal is 8. The maximum value of Ptotal
is 2055. To achieve the minimum value of Ptotal, PB and PO
should both be programmed to 0. To achieve the maximum
value of Ptotal, PB should be programmed to 1023, and PO
should be programmed to 1.
Stable operation of the CY22701 cannot be guaranteed if the
value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below
100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
Table 6. Q Counter Register Definition
Register
42H
D7
PO
D6
Q(6)
D5
Q(5)
D4
Q(4)
D3
Q(3)
D2
Q(2)
D1
Q(1)
D0
Q(0)
Table 7. P Counter Register Definition
Address
40H
41H
D7
1
PB(7)
D6
1
PB(6)
42H PO Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Document #: 38-07698 Rev. *B
Page 5 of 15
5 Page 
PRELIMINARY
CY22701
Absolute Maximum Conditions
Parameter
VDD
TS
TJ
Description
Supply Voltage
Storage Temperature
Junction Temperature
Logic Inputs
I2C interface (SDAT and SCL)
Digital Outputs referred to VDD
Electro-Static Discharge
Endurance (@ 25°C)
Data retention
Min.
–0.5
–65
–40
VSS – 0.5
–0.5
VSS – 0.5
10
Max.
7.0
125
100
VDD + 0.5
5.5
VDD + 0.5
2000
1,000,000 (100k/page)
Unit
V
°C
°C
V
V
V
V
writes
yrs
www.DRateacShoemet4mU.ecnomded Operating Conditions
Parameter
Description
VDD
TA
TA
CLOAD
tPU
Operating Voltage
Ambient Temperature, Industrial grade
Ambient Temperature, Commercial grade
Max. Load Capacitance
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
Min.
Typ.
Max.
Unit
3.135 3.3 3.465 V
–40 –
85 °C
0 – 70 °C
– – 15 pF
0.05 – 500 ms
DC Electrical Specifications
Parameter
IOH
IOL
VIH
VIL
CIN
IIZ
f∆XO
IVDD
ISB
Name
Output High Current[2]
Output Low Current[2]
Input High Voltage
Input Low Voltage
Input Capacitance[2, 3]
Input Leakage Current
VCXO Pullability Range[3]
Supply Current
Supply Current - Power
Down Mode Enabled
Description
VOH = VDD – 0.5, VDD = 3.3V
VOL = 0.5, VDD = 3.3V
CMOS levels
CMOS levels
Except XTAL pins
Current drawn while part is in
standby.
Min.
12
12
0.7 * VDD
–
–
–
+150
–
–
Typ.
–
–
–
–
–
–
–
45
5
Max.
24
24
–
0.3 * VDD
7
10
–
–
40
Unit
mA
mA
V
V
pF
µA
ppm
mA
µA
DC Electrical Specifications – 2.5V Outputs
Parameter
Name
Description
Min.
IOH2.5
IOL2.5
Output High Current[2, 4] VOH = VDD – 0.5, VDD = 3.3 V
Output Low Current[2, 4] VOL = 0.5, VDD = 3.3 V
12
12
Notes:
2. Guaranteed by design, not 100% tested.
3. Crystal must meet Table 14 specifications.
4. VDD is only specified and characterized at 3.3V + 5%. VDDL may be powered at any value between 3.465 and 2.375.
Typ.
–
–
Max.
24
24
Unit
mA
mA
Document #: 38-07698 Rev. *B
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY22701.PDF ] | |
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