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PDF MX29LV002NCT Data sheet ( Hoja de datos )
| Número de pieza | MX29LV002NCT | |
| Descripción | 2M-BIT [256K x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX29LV002C/002NC T/B
2M-BIT [256K x 8] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 262,411 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte Programming (9us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x3)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase operation completion.
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Hardware RESET# pin (only for 29LV002C)
- Resets internal state machine to read mode
• Package type:
- 32-pin TSOP (type 1)
- 32-pin PLCC
• 20 years data retention
GENERAL DESCRIPTION
The MX29LV002C T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits. MXIC's Flash memo-
ries offer the most cost-effective and reliable read/write
non-volatile random access memory. The MX29LV002C
T/B is packaged in 32-pin TSOP and 32-pin PLCC. It is
designed to be reprogrammed and erased in system or
in standard EPROM programmers.
The standard MX29LV002C T/B offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV002C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV002C T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV002C T/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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MX29LV002C/002NC T/B
mand through the command register without requiringVID,
as shown in table4.
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in table3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.
TABLE 3. MX29LV002C T/B AUTOSELECT MODE OPERATION
A17 A12
A8
A5
Description
CE# OE# WE# RESET# | | A9 | A6 | A1 A0 Q7~Q0
(note) A13 A10
A7
A2
Manufacture Code L L H
H X X VID X L X L L
C2H
Read
Device ID
L LH
H X X VID X L X L H
59H
Silicon (Top Boot Block)
ID Device ID
L LH
H X X VID X L X L H
5AH
(Bottom Boot Block)
01H
Sector Protection Verification L L H
H SA X VID X L X H L (protected)
00H
(unprotected)
NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High.
RESET# pin for 32-TSOP only.
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MX29LV002C/002NC T/B
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector erase
is a six-bus cycle operation. There are two "unlock" write
cycles. These are followed by writing the set-up com-
mand 80H. Two more "unlock" write cycles are then fol-
lowed by the sector erase command 30H. The sector
address is latched on the falling edge of WE# or CE#,
whichever happens later, while the command (data) is
latched on the rising edge of WE# or CE#, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE# or
CE#, whichever happens later. Each successive sector
load cycle started by the falling edge of WE# or CE#,
whichever happens later must begin within 50us from
the rising edge of the preceding WE# or CE#, whichever
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
Table 7. Write Operation Status
Status
Q7 Q6 Q5 Q3 Q2 RY/BY#
(Note1)
(Note2)
Byte Program in Auto Program Algorithm
Q7# Toggle 0 N/A No
0
Toggle
Auto Erase Algorithm
0 Toggle 0
1 Toggle 0
In Progress
Erase Suspended Mode
Erase Suspend Read
(Erase Suspended Sector)
1 No 0 N/A Toggle
Toggle
Erase Suspend Read
Data Data Data Data Data
(Non-Erase Suspended Sector)
1
1
Erase Suspend Program
Q7# Toggle 0 N/A N/A
0
Byte Program in Auto Program Algorithm
Exceeded
Time Limits Auto Erase Algorithm
Erase Suspend Program
Q7# Toggle 1
0 Toggle
Q7# Toggle
1
1
N/A No
Toggle
1 Toggle
N/A N/A
0
0
0
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
P/N:PM1204
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| PDF Descargar | [ Datasheet MX29LV002NCT.PDF ] | |
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