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PDF HYB18H512321BF-08 Data sheet ( Hoja de datos )
| Número de pieza | HYB18H512321BF-08 | |
| Descripción | 512-Mbit GDDR3 Graphics RAM | |
| Fabricantes | Qimonda AG | |
| Logotipo |  |
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September 2007
www.DataSheet4U.com
HYB18H512321BF–11/12/14
HYB18H512321BF–08/10
512-Mbit GDDR3 Graphics RAM
GDDR3 Graphics RAM
RoHS compliant
Internet Data Sheet
Rev. 1.1
1 page  
2 Configuration
Internet Data Sheet
www.DataSheet4U.com
HYB18H512321BF
512-Mbit GDDR3
FIGURE 1
Ballout 512-Mbit GDDR3 Graphics RAM [Top View, MF = Low ]
1234
VDDQ
VDD
VSS
ZQ
VSSQ DQ0 DQ1 VSSQ
VDDQ DQ2 DQ3 VDDQ
VSSQ WDQS0 RDQS0 VSSQ
VDDQ DQ4 DM0 VDDQ
VDD DQ6 DQ5 CAS
VSS VSSQ DQ7 BA0
VREF A1 RAS CKE
VSS RFU RFU VDDQ
VDD A10
A2
A0
VSS VSSQ DQ25 A11
VDD DQ24 DQ27 A3
VDDQ DQ26 DM3 VDDQ
VSSQ WDQS3 RDQS3 VSSQ
VDDQ DQ28 DQ29 VDDQ
VSSQ DQ30 DQ31 VSSQ
VDDQ
VDD
VSS SEN
5
67
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
8 9 10 11 12
MF
VSS
VDD
VDDQ
VSSQ DQ9 DQ8 VSSQ
VDDQ DQ11 DQ10 VDDQ
VSSQ RDQS1 WDQS1 VSSQ
VDDQ DM1 DQ12 VDDQ
CS DQ13 DQ14 VDD
BA1 DQ15 VSSQ
VSS
WE BA2 A5 VREF
VDDQ
CK
CK
VSS
A4 A6 A8/AP VDD
A7 DQ17 VSSQ VSS
A9 DQ19 DQ16 VDD
VDDQ DM2 DQ18 VDDQ
VSSQ RDQS2 WDQS2 VSSQ
VDDQ DQ21 DQ20 VDDQ
VSSQ DQ23 DQ22 VSSQ
RESET VSS
VDD
VDDQ
Rev. 1.1, 2007-09
05292007-WAU2-UU95
5
5 Page 
3 Boundary Scan
Internet Data Sheet
www.DataSheet4U.com
HYB18H512321BF
512-Mbit GDDR3
3.1 General Description
The 512Mbit GDDR3 incorporates a modified boundary scan test mode. This mode doesn’t operate in accordance with IEEE
Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input and output the scanned
data through the WDQS0 pin controlled by SEN.
3.2 Disabling the scan feature
It is possible to operate the 512Mbit GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball package) should
be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode,
RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when SEN is deasserted.
BIT#
1
2
3
4
5
6
7
8
9
10
11
12
BALL
D-3
C-2
C-3
B-2
B-3
A-4
B-10
B-11
C-10
C-11
D-10
D-11
BIT#
13
14
15
16
17
18
19
20
21
22
23
24
BALL
E-10
F-10
E-11
G-10
F-11
G-9
H-9
H-10
H-11
J-11
J-10
L-9
BIT#
25
26
27
28
29
30
31
32
33
34
35
36
BALL
K-11
K-10
K-9
M-9
M-11
L-10
N-11
M-10
N-10
P-11
P-10
R-11
BIT#
37
38
39
40
41
42
43
44
45
46
47
48
BALL
R-10
T-11
T-10
T-3
T-2
R-3
R-2
P-3
P-2
N-3
M-3
N-2
BIT#
49
50
51
52
53
54
55
56
57
58
59
60
TABLE 6
Boundary Scan Exit Order
BALL BIT# BALL
L-3 61
M-2 62
M-4 63
K-4 64
K-3 65
K-2 66
L-4 67
J-3
J-2
H-2
H-3
H-4
G-4
F-4
F-2
G-3
E-2
F-3
E-3
Notes
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67,
if the chip stays in scan shift mode.
3. Two RFU balls (#56 and #57) in the scan order, will read as a logic 0.
Rev. 1.1, 2007-09
05292007-WAU2-UU95
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYB18H512321BF-08.PDF ] | |
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