PDF IS42S32800B Data sheet ( Hoja de datos )

Número de pieza	IS42S32800B
Descripción	SYNCHRONOUS DYNAMIC RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS42S32800B ISSI® www.DataSheet4U.com 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM July 2006 FEATURES · Concurrent auto precharge · Clock rate:166/143 MHz · Fully synchronous operation · Internal pipelined architecture · Four internal banks (2M x 32bit x 4bank) · Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write · Burst stop function · Individual byte controlled by DQM0-3 · Auto Refresh and Self Refresh · 4096 refresh cycles/64ms (15.6µs/row) · Single +3.3V ±0.3V power supply · Interface:LVTTL · Package: 86 Pin TSOP-2,0.50mm Pin Pitch 8x13mm, 90 Ball BGA, Ball pitch 0.8mm · Pb-free package is available. DESCRIPTION The ISSI IS42S32800B is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ISSI IS42S32800B provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register,the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/24/06 1 1 page IS42S32800B ISSI® www.DataSheet4U.com PIN CONFIGURATION PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch) 123456789 A DQ26 DQ24 VSS B DQ28 VDDQ VSSQ C VSSQ DQ27 DQ25 D VSSQ DQ29 DQ30 E VDDQ DQ31 NC F VSS DQM3 A3 G A4 A5 A6 H A7 A8 NC J CLK CKE A9 K DQM1 NC NC L VDDQ DQ8 VSS M VSSQ DQ10 DQ9 N VSSQ DQ12 DQ14 P DQ11 VDDQ VSSQ R DQ13 DQ15 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC DQ16 VSSQ A2 DQM2 VDD A10 A0 A1 NC BA1 A11 BA0 CS RAS CAS WE DQM0 VDD DQ7 VSSQ DQ6 DQ5 VDDQ DQ1 DQ3 VDDQ VDDQ VSSQ DQ4 VDD DQ0 DQ2 PIN DESCRIPTIONS A0-A11 A0-A8 BA0, BA1 DQ0 to DQ31 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/24/06 WE DQM0-DQM3 VDD Vss VDDQ VssQ NC Write Enable x32 Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection 5 5 Page IS42S32800B ISSI® www.DataSheet4U.com CLK ADDRESS COMMAND T0 T1 T2 T3 T4 T5 T6 T7 T8 Bank, Col A READ A NOP NOP Bank(s) NOP Precharge tRP NOP NOP Bank, Row Activate NOP CAS# latency=2 tCK2, DQ s CAS# latency=3 tCK3, DQ s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Read to Precharge (CAS#Latency =2,3) 5 Write command (RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A7 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts, the first valid data-in element will be registered coincident with the Write command.Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with high- impedance at the end of the burst unless another command is initiated.The burst length and burst sequence are determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). CLK COMMAND T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP WRITEA NOP NOP NOP NOP NOP NOP NOP DQ0 - DQ3 DIN A 0 DIN A1 DIN A 2 DIN A 3 don’t care The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length =4,CAS#Latency =2,3) A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/ PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/24/06 11 11 Page

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Número de pieza	Descripción	Fabricantes
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IS42S32800D	8M x 32 256Mb SYNCHRONOUS DRAM	Integrated Silicon Solution
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