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PDF HT48E10 Data sheet ( Hoja de datos )
| Número de pieza | HT48E10 | |
| Descripción | I/O Type 8-Bit MTP MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT48E10www.DataSheet4U.com
I/O Type 8-Bit MTP MCU With EEPROM
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0086E HT48E MCU Series - Using Assembly Language to Write to the 1K EEPROM Data Memory
- HA0087E HT48E MCU Series - Using C Language to Write to the 1K EEPROM Data Memory
- HA0088E HT48E MCU Series - Using Assembly Language to Write to the 2K EEPROM Data Memory
- HA0089E HT48E MCU Series - Using C Language to Write to the 2K EEPROM Data Memory
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Low voltage reset function
· 19 bidirectional I/O lines (max.)
· Interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 1,000 erase/write cycles MTP program memory
· 1024´14 program memory ROM (MTP)
· 128´8 data memory EEPROM
· 64´8 data memory RAM
· Buzzer driving pair and PFD supported
· HALT function and wake-up feature reduce power
consumption
· 4-level subroutine nesting
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· 106 erase/write cycles EEPROM data memory
· EEPROM data retention > 10 years
· All instructions in one or two machine cycles
· In system programming (ISP)
· 24-pin SKDIP/SOP package
General Description
The HT48E10 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Rev. 1.50
1 October 31, 2006
1 page  
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Functional Description
Execution Flow
The HT48E10 system clock is derived from either a
crystal or an RC oscillator and is internally divided into
four non-overlapping clocks. One instruction cycle con-
sists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
This pipelining scheme ensures that instructions are ef-
fectively executed in one cycle. If an instruction changes
the contents of the program counter, such as subroutine
calls or jumps, in which case, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading into the PCL register, subroutine call or
return from subroutine, initial reset, internal interrupt,
external interrupt or return from interrupt, the PC man-
ages the program transfer by loading the address corre-
sponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Initial Reset
External Interrupt
Timer/Event Counter Overflow
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
*9
0
0
0
*9
#9
S9
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
Program Counter
*8 *7 *6 *5 *4 *3 *2 *1 *0
000000000
000000100
000001000
Program Counter+2
*8 @7 @6 @5 @4 @3 @2 @1 @0
#8 #7 #6 #5 #4 #3 #2 #1 #0
S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
S9~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.50
5 October 31, 2006
5 Page 
wwHwT.D4a8taES1he0et4U.com
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, a regular interrupt re-
sponse takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system clock pe-
riod) to resume to normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The time-out during HALT is different from other chip re-
set conditions, since it can perform a ²warm reset² that
resets only the Program Counter and Stack Pointer,
leaving the other circuits in their original state. Some
registers remain unchanged during other reset condi-
tions. Most registers are reset to the ²initial condition²
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset Timing Chart
V DD
0 .0 1 m F *
100kW
10kW
RES
0 .1 m F *
Reset Circuit
Note: ²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
H A LT
W DT
W a rm R e s e t
RES
O SC1
SST
1 0 - b it R ip p le
C o u n te r
C o ld
R eset
S y s te m R e s e t
Reset Configuration
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able an SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
Rev. 1.50
11 October 31, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT48E10.PDF ] | |
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