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PDF HYB18H1G321AF-10 Data sheet ( Hoja de datos )
| Número de pieza | HYB18H1G321AF-10 | |
| Descripción | GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM | |
| Fabricantes | Qimonda AG | |
| Logotipo |  |
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October 2007
www.DataSheet4U.com
HYB18H1G321AF–10/11/14
GDDR3 Graphics RAM
1-Gbit GDDR3 Graphics RAM
RoHS compliant
Internet Data Sheet
Rev. 0.92
1 page  
2 Configuration
Internet Data Sheet
www.DataSheet4U.com
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 1
Ballout 1Gbit GDDR3 Graphics RAM in 1-CS mode in non Merged Mode(Top View; MF = Low)
9''4
9''
966
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966 9664 '4 %$
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Rev. 0.92, 2007-10
06122007-MW7D-3G3M
5
5 Page 
2.3 Truth Tables
Internet Data Sheet
www.DataSheet4U.com
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
2.3.1
Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the
chip’s multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions
are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the
assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD,
tRTW and tWTR have to be taken always into account.
TABLE 4
Function Truth Table I
Current State
Ongoing action on bank n
Possible action in parallel on bank m
ACTIVE
ACTIVATE1)
WRITE3)
WRITE/A5)
READ7)
READ/A9)
PRECHARGE10)
PRECHARGE ALL 10)
POWER DOWN ENTRY12)
ACT, PRE, WRITE, WRITE/A, READ, READ/A2)
ACT, PRE, WRITE, WRITE/A, READ, READ/A4)
ACT, PRE, WRITE, WRITE/A, READ6)
ACT, PRE, WRITE, WRITE/A, READ, READ/A8)
ACT, PRE, WRITE, WRITE/A, READ, READ/A 8)
ACT, PRE, WRITE, WRITE/A, READ, READ/A11)
-
-
IDLE
ACTIVATE 1)
ACT
POWER DOWN ENTRY 12)
-
AUTO REFRESH13)
-
SELF REFRESH ENTRY 12)
-
MODE REGISTER SET (MRS)14)
-
EXTENDED MRS 14)
-
EXTENDED MRS 214)
-
POWER DOWN
POWER DOWN EXIT15)
-
SELF REFRESH
SELF REFRESH EXIT16)
-
1) Action ACTIVATE starts with issuing the command and ends after tRCD.
2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD or tRRD_RR, a PRE command on another bank is
allowed any time. WR, WR/A, RD and RD/A are always allowed.
3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge.
4) During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR or tWTR_RR is met.
5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge.
6) During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
has to be separated by at least one NOP from the ongoing command. RD is not allowed before or tWTR or tWTR_RR is met. RD/A is not
allowed during an ongoing WRITE/A action.
7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
8) During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on
another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to
meet tRTW.
9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
11
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet HYB18H1G321AF-10.PDF ] | |
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