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PDF TSL1402R Data sheet ( Hoja de datos )
| Número de pieza | TSL1402R | |
| Descripción | 256 x 1 LINEAR SENSOR ARRAY WITH HOLD | |
| Fabricantes | TAOS | |
| Logotipo |  |
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D 256 × 1 Sensor-Element Organization
D 400 Dots-Per-Inch (DPI) Sensor Pitch
D High Linearity and Uniformity
D Wide Dynamic Range . . . 4000:1 (72 dB)
D Output Referenced to Ground
D Low Image Lag . . . 0.5% Typ
D Operation to 8 MHz
D Single 3-V to 5-V Supply
D Rail-to-Rail Output Swing (AO)
D No External Load Resistor Required
D Replacement for TSL1402
TSL1402R
256 × 1 LINEAR SENSOR ARRAY WITH HOLD
www.DTaAtOaSS0h4e1Fet−4AUP.cRoILm2007
VDD 1
SI1 2
CLK 3
AO1 4
GND 5
SO2 6
NC 7
ÉÉÉÉÉÇÇÇÇÇ(TOP VIEW)
14 NC
13 SO1
12 GND
11 NC
10 SI2
9 NC
8 AO2
NC − No internal connection
Description
The TSL1402R linear sensor array consists of two sections of 128 photodiodes each and associated charge
amplifier circuitry, aligned to form a contiguous 256 × 1 pixel array. The device incorporates a pixel data-hold
function that provides simultaneous integration start and stop times for all pixels. The pixels measure 63.5 μm
by 55.5 μm, with 63.5-μm center-to-center spacing and 8-μm spacing between pixels. Operation is simplified
by internal logic requiring only a serial-input pulse (SI) and a clock.
The TSL1402R is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram (each section − pin numbers apply to section 1)
Pixel 1
1 Integrator
S1 2 Reset
2
_1
+ S2
Sample/Hold/
Output
3
Pixel
2
Pixel
3
Pixel
128
Analog
Bus
Output
Buffer
Hold
Q1
Switch Control Logic
Q2
Q3
Q128
Gain
Trim
1 VDD
4
AO
5
GND
13 SO
CLK 3
SI 2
128-Bit Shift Register
The
LUMENOLOGY
r
Company
Texas
Advarnced
Optoelectronic
Solutions
Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972r) 673-0759
www.taosinc.com
Copyright E 2007, TAOS Inc.
1
1 page  
TSL1402R
256 × 1 LINEAR SENSOR ARRAY WITH HOLD
www.DTaAtOaSS0h4e1Fet−4AUP.cRoILm2007
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 11 μW/cm2 (unless otherwise noted) (see Note 3)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Vout
Vdrk
PRNU
Analog output voltage (white, average over 256 pixels)
Analog output voltage (dark, average over 256 pixels)
Pixel response nonuniformity
See Note 4
Ee = 0
See Note 5
1.6
2 2.4
V
0 0.1 0.2 V
± 10%
Nonlinearity of analog output voltage
See Note 6
± 0.4%
Output noise voltage
See Note 7
1 mVrms
Re Responsivity
See Note 8
25
35
45
V/
(μJ/cm2)
Vsat Analog output saturation voltage
SE Saturation exposure
DSNU Dark signal nonuniformity
IL Image lag
VDD = 5 V, RL = 330 Ω
VDD = 3 V, RL = 330 Ω
VDD = 5 V, See Note 9
VDD = 3 V, See Note 9
All pixels, Ee = 0, See Note 10
See Note 11
4.5 4.8
2.5 2.8
V
136
78
nJ/cm2
0.04 0.12
V
0.5%
IDD Supply current
IIH High-level input current
IIL Low-level input current
Ci Input capacitance, SI
VDD = 5 V, Ee = 0
VDD = 3 V, Ee = 0
VI = VDD
VI = 0
69
5 8 mA
10 μA
10 μA
5 pF
Ci Input capacitance, CLK
10 pF
NOTES: 3. All measurements made with a 0.1 μF capacitor connected between VDD and ground.
4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
8. Re(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint)
9. SE(min) = [Vsat(min) − Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) − Vdrk(min)]
10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
+
Vout (IL) * Vdrk
Vout (white) * Vdrk
100
Timing Requirements (see Figure 1 and Figure 2)
tsu(SI) Setup time, serial input (see Note 12)
th(SI) Hold time, serial input (see Note 12 and Note 13)
tw Pulse duration, clock high or low
tr, tf Input transition (rise and fall) time
tqt Pixel charge transfer time
NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
13. SI must go low before the rising edge of the next clock pulse.
MIN NOM MAX UNIT
20 ns
0 ns
50 ns
0 500 ns
20 μs
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2007, TAOS Inc.
5
5 Page 
TSL1402R
256 × 1 LINEAR SENSOR ARRAY WITH HOLD
APPLICATION INFORMATION
www.DTaAtOaSS0h4e1Fet−4AUP.cRoILm2007
The minimum integration time can be calculated from the equation:
ǒ ǓTint(min) +
1
maximum clock frequency
(n * 18) pixels ) 20ms
where:
n
is the number of pixels
In the case of the TSL1402R with the maximum clock frequency of 8 MHz, the minimum integration time would
be:
Tint(min) + 0.125 ms (128 * 18) ) 20 ms + 33.75 ms
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
It should be noted that the data from the light sampled during one integration period is made available on the
analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock
period. In other words, at any given time, two groups of data are being handled by the linear array: the previous
measured light data is clocked out as the next light sample is being integrated.
Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2007, TAOS Inc.
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet TSL1402R.PDF ] | |
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