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PDF MAX2741 Data sheet ( Hoja de datos )
| Número de pieza | MAX2741 | |
| Descripción | Integrated L1-Band GPS Receiver | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3559; Rev 0; 1/05
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Integrated L1-Band GPS Receiver
General Description
The MAX2741 L1-band GPS receiver IC offers a high-
performance, compact solution for mobile handsets,
PDAs, and automotive applications. Total voltage gain
of 80dB and a 4.7dB cascaded noise figure can pro-
vide receiver sensitivity for applications requiring
-185dBW for indoor tracking solutions.
This dual-conversion receiver downconverts the
1575.42MHz GPS signal to a 37.38MHz first IF, and then
a 3.78MHz second IF. An integrated 2- or 3-bit ADC (1-
bit SIGN, 1- or 2-bit MAG selectable) samples the sec-
ond IF and outputs the digitized signals to the baseband
processor.
The integrated synthesizer offers the flexibility in fre-
quency planning to allow a single board design to be
employed for reference frequencies from 2MHz to
26MHz. The integrated reference oscillator allows either
TCXO or crystal operation.
The receiver runs from a 2.7V to 3.0V supply, and draws
only 30mA when active. It is offered in a 28-pin thin QFN
package, and is specified for -40°C to +85°C at 3V.
PIN THIN Q
0mm x 5.0m
Applications
In-Vehicle Navigation Systems (IVNS)
Telematics (Vehicle and Asset Tracking,
Inventory Management)
Automotive Security
Emergency Response Systems
Emergency Road-Side Assistance
Location-Based Services/Internet (PDAs)
Digital Cameras/Camcorders
Recreational Handhelds/Walkie-Talkies
Geographical Information Systems (GIS)
Consumer Electronics (Location-Based Games)
Precision Timing
Features
♦ Supports All Popular Handset Reference
Frequencies Up to 26MHz
♦ 4.7dB Cascaded Noise Figure
♦ 80dB Cascaded Gain
♦ Tolerates -90dBm In-Band Jammer
♦ Tolerates +13dBm CDMA Out-of-Band Jammer at
Device Input
♦ Integrated Synthesizer and VCO
♦ Integrated 2- or 3-Bit ADC
♦ 50dB IF AGC Range
♦ Small 28-Pin Thin QFN Package
♦ SPI™ Control Interface
♦ Clock Output for Baseband Processor
SPI is a trademark of Motorola, Inc.
PART
MAX2741ETI
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
28 Thin QFN
Pin Configuration/
Functional Diagram
VCC1 1
28 27 26 25 24 23 22
Σ MAX2741
21 SDO
N.C. 2
RFIN 3
LNA
1612.8MHz 90 /2
VCC2 4
VCC3 5
VCC4 6
VCO
3225.6MHz
33.6MHz
0 /96
/16128
ADC
P.D.
200kHz
/R
/192
MUX
16.8MHz
20 N.C.
19 VCC5
18 GPSIF0
17 GPSIF1
16 GPSIF2
GND 7
SPI INTERFACE
REF
OSC
15 GPSCLK
8 9 10 11 12 13 14
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Integrated L1-Band GPS Receiver
Detailed Description
The MAX2741 GPS offers a high-performance super-
heterodyne receiver solution for low-power mobile
devices, with the benefit of using the system’s existing
clock reference. This receiver is ideal for integration into
mobile phone handsets using common reference fre-
quencies such as 10.0, 13.0, 14.4, 19.2, 20.0, and
26.0MHz. The only external components required are the
GPS RF filter, an IF filter (typically designed from inexpen-
sive discretes), a three-component PLL loop filter, and a
few other resistors and capacitors. The MAX2741 inte-
grates the reference oscillator core, the VCO and its tank,
the synthesizer, a 1- to 3-bit ADC, and all signal path
blocks except for the 1st IF filter. The typical application
area for the receiver is less than 2cm2.
RF/1st Conversion Stage (Front-End)
The MAX2741 RF front-end LNA and mixer are the most
important in the signal path. This stage sets the noise
figure for the receiver, defining the sensitivity, and mixes
the 1575.42MHz L1-band GPS signal down to a 1st IF of
37.38MHz. The LNA itself has an NF of approximately
1.5dB; the cascaded NF of the front-end (including the
mixer) is approximately 4.7dB, and the cascaded gain
is typically 21dB.
The image-reject mixer is set up for a high-side injected
RFLO (1612.80MHz), and offers typically better than 30dB
rejection of the image noise (1650.18MHz). The -30dBm
input 3rd-order intercept (IIP3) of the RF strip, in conjunc-
tion with the GPS IF filter, provides excellent out-of-band
interferer immunity.
The 1st IF outputs (IFOUT±) are internally biased to
approximately 2V, and have a differential source
impedance of approximately 2.5kΩ. The IF filter can be
implemented as a discrete L/C filter, or as a monolithic
SAW or ceramic if one is available.
IF/2nd Conversion Stage
The 2nd conversion stage consists of an active mixer, a
variable-gain amplifier (VGA), and a tunable lowpass
filter. The IF mixer is configured for low-side LO injec-
tion for a 2nd IF of 3.78MHz. Total gain in this stage is
62dB, and the VGA offers 51dB of gain adjustment. The
VGA is typically controlled by the baseband IC through
the SPI interface to optimize the signal swing for digiti-
zation by the ADC.
The on-chip lowpass filter has an adjustable cutoff fre-
quency, programmable from 2.9MHz to 7.7MHz in 16
steps. This LPF further reduces out-of-band noise and
band-limits the signal to the ADC, ensuring that the
sampling process does not generate alias components.
DC offset compensation at the ADC input is performed by
an on-chip 4-bit DAC. This compensates for any DC error
introduced by transistor mismatch in the differential stage
driving the ADC input, allowing the downconverted GPS
signal’s DC level to be centered within the threshold volt-
ages of the ADC.
ADC
The on-chip ADC samples the down-converted GPS
signal at the 2nd IF (3.78MHz). Sampled output is pro-
vided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit
(2-bit magnitude, 1-bit sign) formats, as determined by
the ADC mode configuration bit (CONFIG1:D15); see
Table 5 for details. The ADC sample clock (system GPS
clock) is derived either directly from the reference clock
(SYNTH:D9 = 1), or from an RFLO divide-by-96 block to
provide a 16.8MHz sample clock (SYNTH:D9 = 0). The
clock is available to the baseband processor at
GPSCLK (pin 15). The sampled ADC data bits are
available on pins 16, 17, and 18 (GPSIF2, GPSIF1, and
GPSIF0). The functionality of the pins is different in
each mode (2-bit vs. 3-bit)—see Table 5 in determining
the interface connection for the application circuit.
Synthesizer
The MAX2741 integrates an integer-N synthesizer; all
blocks except the loop filter are on-chip. The reference
can be either a crystal (driven by the internal oscillator),
or a TCXO module. The oscillator provides a 5pF load
to the crystal. A TCXO module should provide a swing
in the 0.6VP-P to 2.2VP-P range.
The reference divider (/R) is programmable (SYNTH:
D7–D0), and can accommodate reference frequencies
up to 26MHz. The reference divider needs to be set so
the comparison frequency (fCOMP) at the frequency/
phase detector is 200kHz. The VCO runs at twice the fre-
quency of the RFLO; the RFLO is therefore generated
from the VCO using a quadrature divide-by-2 block. The
RF LO is fCOMP x 8064 (typically 1612.80MHz), and the
1st IF LO is fCOMP x 168 (typically 33.6MHz); the RF and
IF LO division ratios are not adjustable. This configuration
allows for the use of reference frequencies common to
GSM, CDMA, TDMA, TD-SCDMA, and UMTS handsets:
9.6MHz (R = 48), 13.0MHz (R = 65), 14.4MHz (R = 72),
19.2MHz (R = 96), 26.0MHz (R = 130), etc.
_______________________________________________________________________________________ 5
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Integrated L1-Band GPS Receiver
100pF
22pF
Typical Application Circuit
VCC
680pF
5.6pF
680pF
39pF
470µH
470µH
39pF
680pF
5.6pF
680pF
VCC
GPS RF INPUT
FROM GPS BPF
VCC
VCC
VCC
100pF
22pF
100pF
2.2pF
6.2nH
100pF
22pF
1nF 100pF
100nF
100pF
28 27 26 25 24 23 22
VCC1 1
Σ
MAX2741
N.C.
2
RFIN
3
LNA
1612.8MHz 90 /2
VCC2 4
VCC3 5
VCC4 6
VCO
3225.6MHz
33.6MHz
0 /96
/16128
ADC
P.D.
200kHz
/R
/192
MUX
16.8MHz
GND
7
SPI INTERFACE
REF
OSC
8 9 10 11 12 13 14
SDO
21
N.C.
20
19 VCC5
GPSIF0
18
GPSIF1
17
GPSIF2
16
GPSCLK
15
100pF
SPI DATA OUT
TO BASEBAND PROCESSOR
VCC
1nF
GPS DATA AND CLOCK
TO BASEBAND PROCESSOR
22nF
36kΩ
100pF
220pF
SPI CLOCK AND DATA INTO
BASEBAND PROCESSOR
H/W SHUTDOWN LINE
FROM BASEBAND PROCESSOR
SYSTEM TCXO
(2MHz TO 26MHz)
Table 9. Digital Test-Mode-Select Description
MODE
3
2
1
0
REGISTER SETTING
CONFIG1:D9 to D8
11
10
01
00
GPSIF2
SIGN
M COUNTER
CHARGE PUMP UP
CML CLOCK
DIGITAL OUTPUT FUNCTION
GPSIF1
LSB
R COUNTER
CHARGE PUMP DOWN
CALIBRATE LPF END
GPSIF0
MSB
HANDSHAKE STATUS
SDO
XTL CLOCK SELECTED
Digital Test Bus
The digital test bus (DTB) is provided to allow for easy
bench analysis of the digital workings of the receiver.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX2741.PDF ] | |
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