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PDF CY7C68053 Data sheet ( Hoja de datos )
| Número de pieza | CY7C68053 | |
| Descripción | MoBL-USB FX2LP18 USB Microcontroller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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MoBL-USB™ FX2LP18 USB
Microcontroller
1. CY7C68053 Features
■ USB 2.0 – USB-IF High-Speed and Full-Speed Compliant
(TID# 40000188)
■ Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
■ Ideal for mobile applications (cell phone, smart phones,
PDAs, MP3 players)
❐ Ultra low power
❐ Suspend current: 20 µA (typical)
■ Software: 8051 code runs from:
❐ Internal RAM, which is loaded from EEPROM
■ 16 kBytes of on-chip Code/Data RAM
■ Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
❐ Buffering options: double, triple, and quad
■ Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
■ 8- or 16-bit external data interface
■ Smart Media Standard ECC generation
■ GPIF (General Programmable Interface)
❐ Allows direct connection to most parallel interface
❐ Programmable waveform descriptors and configuration reg-
isters to define waveforms
❐ Supports multiple Ready and Control outputs
■ Integrated, industry standard enhanced 8051
❐ 48 MHz, 24 MHz, or 12 MHz CPU operation
❐ Four clocks per instruction cycle
❐ Three counter/timers
❐ Expanded interrupt system
❐ Two data pointers
■ 1.8V Core operation
■ 1.8V - 3.3V IO operation
■ Vectored USB interrupts and GPIF/FIFO interrupts
■ Separate data buffers for the Setup and Data portions of a
CONTROL transfer
■ Integrated I2C™ controller, runs at 100 or 400 kHz
■ Four integrated FIFOs
❐ Integrated glue logic and FIFOs lower system cost
❐ Automatic conversion to and from 16-bit buses
❐ Master or slave operation
❐ Uses external clock or asynchronous strobes
❐ Easy interface to ASIC and DSP ICs
■ Available in Industrial temperature grade
■ Available in one Pb-free package with up to 24 GPIOs
❐ 56-pin VFBGA (24 GPIOs)
Block Diagram
24 MHz
Ext. XTAL
High-performance microprocessor
using standard tools
with lower-power options
MoBL-USB FX2LP18
VCC
/0.5
x20
/1.0
PLL /2.0
1.5K
Connected for
Full-Speed
D+
D–
Integrated
Full- and High-Speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
8051 Core
12/24/48 MHz,
Four Clocks/Cycle
16 KB
RAM
I2C
Master
Additional IOs (24)
ECC
GPIF
RDY (2)
CTL (3)
4 KB
FIFO
8/16
Abundant IO
General
Programmable I/F
To Baseband Processors/
Application Processors/
ASICS/DSPs
Up to 96 MBytes/sec
Burst Rate
Enhanced USB Core
Simplifies 8051 Code
“Soft Configuration”
Easy Firmware Changes
FIFO and Endpoint Memory
(Master or Slave Operation)
Cypress Semiconductor Corporation • 198 Champion Court
Document # 001-06120 Rev *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 6, 2007
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Figure 2. Reset Timing Plots
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RESET#
VCC
VIL
1.8V
1.62V
TRESET
Power on Reset
0V
RESET#
VCC
VIL
1.8V
TRESET
Powered Reset
0V
3.9 Reset and Wakeup
The reset and wakeup pins are described in detail in this section.
3.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP18 when asserted.
This pin has hysteresis and is active LOW. When a crystal is
used with the CY7C68053, the reset period must allow for the
stabilization of the crystal and the PLL. This reset period must be
approximately 5 ms after VCC has reached 3.0V. If the crystal
input pin is driven by a clock signal the internal PLL stabilizes in
200 μs after VCC has reached 3.0V[2]. Figure 2 shows a power
on reset condition and a reset applied during operation. A power
on reset is defined as the time reset is asserted while power is
being applied to the circuit. A powered reset is defined as a reset
in which the FX2LP18 has previously been powered on and
operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation, which can be
found on the Cypress web site. For more information on reset
implementation for the MoBL-USB family of products, visit the
Cypress web site at http://www.cypress.com.
Table 3. Reset Timing Values
Condition
Power on reset with crystal
Power on reset with external
clock
Powered reset
TRESET
5 ms
200 μs + Clock stability time
200 μs
3.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
wakeup interrupt. This applies whether or not FX2LP18 is
connected to the USB.
The FX2LP18 exits the power down (USB suspend) state using
one of the following methods:
■ USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP18 and initiate a
wakeup)
■ External logic asserts the WAKEUP pin
■ External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general purpose IO pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is active LOW by default.
3.9.3 Lowering Suspend Current
Good design practices for CMOS circuits dictate that any unused
input pins must not be floating between VIL and VIH. Floating
input pins will not damage the chip, but can substantially
increase suspend current. To achieve the lowest suspend
current, confiigure unused port pins as outputs. Connect unused
input pins to ground. Some examples of pins that need attention
during suspend are:
■ Port pins. For Port A, B, D pins, take extra care in shared bus
situations.
❐ Connect completely unused pins to VCC_IO or GND.
❐ In a single-master system, the firmware must output enable
all the port pins and drive them high or low, before FX2LP18
enters the suspend state.
❐ In a multi-master system (FX2LP18 and another processor
sharing a common data bus), when FX2LP18 is suspended,
the external master must drive the pins high or low. The ex-
ternal master must not let the pins float.
■ CLKOUT. If CLKOUT is not used, it must be tri-stated during
normal operation, but driven during suspend.
■ IFCLK, RDY0, RDY1. These pins must be pulled to VCC_IO or
GND or driven by another chip.
Note
2. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 μs.
Document # 001-06120 Rev *H
Page 5 of 39
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Figure 7. CY7C68053 56-pin VFBGA Pin Assignment - Top View
12345678
A 1A 2A 3A 4A 5A 6A 7A 8A
B 1B 2B 3B 4B 5B 6B 7B 8B
C 1C 2C 3C 4C 5C 6C 7C 8C
D 1D 2D
7D 8D
E 1E 2E
7E 8E
F 1F 2F 3F 4F 5F 6F 7F 8F
G 1G 2G 3G 4G 5G 6G 7G 8G
H 1H 2H 3H 4H 5H 6H 7H 8H
Document # 001-06120 Rev *H
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| PDF Descargar | [ Datasheet CY7C68053.PDF ] | |
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