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Número de pieza | RD74VT1G126 | |
Descripción | Bus Buffer Gate with 3-state output / Dual Supply Voltage Translator | |
Fabricantes | Renesas Technology | |
Logotipo | ||
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Bus Buffer Gate with 3-state Output /
Dual Supply Voltage Translator
REJ03D0517–0100
Rev.1.00
Jun. 01, 2005
Description
The RD74VT1G126 has a bus buffer gate with 3-state output in a 6 pin package. Output is disabled when the
associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE
should be connected to GND through a pull-down resistor; the minimum value of the resistor is determined by the
current sourcing capability of the driver. The input is designed to track VCCIN, which accepts voltages from 1.2V to
3.6V, and the output is designed to track VCCOUT, which operates at 1.2V to 3.6V. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption
extends the battery life.
Features
• This product function as level shift that change VCCIN input level to VCCOUT output level by providing different
supply voltage to VCCIN and VCCOUT.
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Supply voltage range: VCCIN = 1.2V to 3.6 V
VCCOUT = 1.2 V to 3.6 V
Operating temperature range: −40 to +85°C
• All inputs VIH (Max.) = 3.6 V (@VCCIN = 0 V to 3.6 V)
Outputs VO (Max.) = 3.6 V (@VCCOUT = 0 V)
• Output current ±2 mA (@VCCOUT = 1.2 V)
±4 mA (@VCCOUT = 1.4 V to 1.6 V)
±6 mA (@VCCOUT = 1.65 V to 1.95 V)
±18 mA (@VCCOUT = 2.3 V to 2.7 V)
±24 mA (@VCCOUT = 3.0 V to 3.6 V)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
RD74VT1G126CLE
WCSP-6 pin
SXBG0006KB–A
(TBS–6AV)
CL E (3,000 pcs/reel)
Article Indication
Marking
Year code
VCYM
Month code
Rev.1.00 Jun. 01, 2005 page 1 of 9
1 page RD74VT1G126
Switching Characteristics (Cont)
Item
Propagation
delay time
Output
enable time
Output
disable time
VCCOUT=
From To
1.2 V
Symbol (input) (output) Typ
tPLH A
Y
9.2
tPHL 9.2
tZH OE
Y
10.5
tZL 10.5
tHZ OE
Y
9.5
tLZ 9.5
VCCOUT=
1.5±0.1 V
Min Max
2.0 9.0
2.0 9.0
2.0 10.2
2.0 10.2
2.0 9.0
2.0 9.0
Ta = –40 to 85°C
VCCOUT=
1.8±0.15 V
VCCOUT=
2.5±0.2 V
Min Max Min Max
1.5 5.8 1.0 4.0
1.5 5.8 1.0 4.0
1.5 6.6 1.0 4.5
1.5 6.6 1.0 4.5
1.5 7.0 1.0 5.2
1.5 7.0 1.0 5.2
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VCCIN = 2.5±0.2 V
VCCOUT=
3.3±0.3 V
Min Max
1.0 3.4
1.0 3.4
1.0 3.5
1.0 3.5
1.0 5.0
1.0 5.0
Test
Unit conditions
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
Item
Propagation
delay time
Output
enable time
Output
disable time
VCCOUT=
From To
1.2 V
Symbol (input) (output) Typ
tPLH A
tPHL
tZH OE
Y
Y
9.5
9.5
10.6
tZL 10.6
tHZ OE
Y
9.5
tLZ 9.5
VCCOUT=
1.5±0.1 V
Min Max
2.0 9.2
2.0 9.2
2.0 10.6
2.0 10.6
2.0 9.5
2.0 9.5
Ta = –40 to 85°C
VCCOUT=
1.8±0.15 V
VCCOUT=
2.5±0.2 V
Min Max Min Max
1.5 6.2 1.0 4.4
1.5 6.2 1.0 4.4
1.5 7.0 1.0 4.8
1.5 7.0 1.0 4.8
1.5 7.4 1.0 5.7
1.5 7.4 1.0 5.7
VCCIN = 1.8±0.15 V
VCCOUT=
3.3±0.3 V
Min Max
1.0 3.9
1.0 3.9
1.0 4.0
1.0 4.0
1.0 5.5
1.0 5.5
Test
Unit conditions
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
Item
Propagation
delay time
Output
enable time
Output
disable time
VCCOUT=
From To
1.2 V
Symbol (input) (output) Typ
tPLH A
Y
9.7
tPHL 9.7
tZH OE
Y
11.2
tZL
tHZ OE
tLZ
Y
11.2
10.0
10.0
VCCOUT=
1.5±0.1 V
Min Max
2.0 9.8
2.0 9.8
2.0 11.2
2.0 11.2
2.0 10.0
2.0 10.0
Ta = –40 to 85°C
VCCOUT=
1.8±0.15 V
VCCOUT=
2.5±0.2 V
Min Max Min Max
1.0 7.0 1.0 4.6
1.0 7.0 1.0 4.6
1.0 7.8 1.0 5.0
1.0 7.8 1.0 5.0
1.0 8.0 1.0 5.8
1.0 8.0 1.0 5.8
VCCIN = 1.5±0.1 V
VCCOUT=
3.3±0.3 V
Min Max
1.0 4.4
1.0 4.4
1.0 4.2
1.0 4.2
1.0 5.9
1.0 5.9
Test
Unit conditions
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
Item
Propagation
delay time
Output
enable time
Output
disable time
From To
Symbol (input) (output)
tPLH A
tPHL
tZH OE
tZL
tHZ OE
tLZ
Y
Y
Y
VCCOUT=
1.2 V
Typ
10.2
10.2
11.6
11.6
10.5
10.5
Ta = –40 to 85°C
VCCOUT=
1.5±0.1 V
VCCOUT=
1.8±0.15 V
VCCOUT=
2.5±0.2 V
Typ Typ Typ
7.5 6.0 4.5
7.5 6.0 4.5
8.5 6.5 5.0
8.5 6.5 5.0
8.2 7.2 6.0
8.2 7.2 6.0
VCCIN = 1.2 V
VCCOUT=
3.3±0.3 V
Typ
4.0
4.0
4.2
4.2
5.7
5.7
Test
Unit conditions
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
Rev.1.00 Jun. 01, 2005 page 5 of 9
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet RD74VT1G126.PDF ] |
Número de pieza | Descripción | Fabricantes |
RD74VT1G125 | Bus Buffer Gate with 3-state output / Dual Supply Voltage Translator | Renesas Technology |
RD74VT1G126 | Bus Buffer Gate with 3-state output / Dual Supply Voltage Translator | Renesas Technology |
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