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PDF PI7C8148A Data sheet ( Hoja de datos )
| Número de pieza | PI7C8148A | |
| Descripción | 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI7C8148A
2-Port PCI-to-PCI Bridge
REVISION 1.04
3545 North First Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Email: [email protected]
Internet: http://www.pericom.com
1 page  
PI7C8148A
2-PORT PCI-TO-PCI BRIDGE
ADVANCE IwNwFwO.RDaMtaASTheIOetN4U.com
TABLE OF CONTENTS
1 SIGNAL DEFINITIONS.............................................................................................................................13
1.1 SIGNAL TYPES....................................................................................................................................13
1.2 SIGNALS ..............................................................................................................................................13
1.2.1 PRIMARY BUS INTERFACE SIGNALS ...................................................................................13
1.2.2 SECONDARY BUS INTERFACE SIGNALS .............................................................................14
1.2.3 CLOCK SIGNALS ........................................................................................................................16
1.2.4 MISCELLANEOUS SIGNALS ....................................................................................................16
1.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS .................................................................17
1.2.6 POWER AND GROUND..............................................................................................................17
1.3 PIN LIST – 160-PIN LFBGA.................................................................................................................18
2 PCI BUS OPERATION...............................................................................................................................19
2.1 TYPES OF TRANSACTIONS ..............................................................................................................19
2.2 SINGLE ADDRESS PHASE.................................................................................................................20
2.3 DEVICE SELECT (DEVSEL#) GENERATION ..................................................................................20
2.4 DATA PHASE.......................................................................................................................................20
2.5 WRITE TRANSACTIONS....................................................................................................................20
2.5.1 MEMORY WRITE TRANSACTIONS.........................................................................................21
2.5.2 MEMORY WRITE AND INVALIDATE .....................................................................................22
2.5.3 DELAYED WRITE TRANSACTIONS ........................................................................................22
2.5.4 WRITE TRANSACTION BOUNDARIES...................................................................................23
2.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS..............................................................23
2.5.6 FAST BACK-TO-BACK TRANSACTIONS ................................................................................23
2.6 READ TRANSACTIONS .....................................................................................................................24
2.6.1 PREFETCHABLE READ TRANSACTIONS .............................................................................24
2.6.2 DYNAMIC PREFETCHING CONTROL....................................................................................24
2.6.3 NON-PREFETCHABLE READ TRANSACTIONS ...................................................................24
2.6.4 READ PREFETCH ADDRESS BOUNDARIES ........................................................................25
2.6.5 DELAYED READ REQUESTS ...................................................................................................25
2.6.6 DELAYED READ COMPLETION WITH TARGET .................................................................26
2.6.7 DELAYED READ COMPLETION ON INITIATOR BUS.........................................................26
2.6.8 FAST BACK-TO-BACK READ TRANSACTIONS ....................................................................27
2.7 CONFIGURATION TRANSACTIONS................................................................................................27
2.7.1 TYPE 0 ACCESS TO PI7C8148A................................................................................................28
2.7.2 TYPE 1 TO TYPE 0 CONVERSION ...........................................................................................28
2.7.3 TYPE 1 TO TYPE 1 FORWARDING ..........................................................................................29
2.7.4 SPECIAL CYCLES.......................................................................................................................30
2.8 TRANSACTION TERMINATION.......................................................................................................30
2.8.1 MASTER TERMINATION INITIATED BY PI7C8148A ..........................................................31
2.8.2 MASTER ABORT RECEIVED BY PI7C8148A .........................................................................32
2.8.3 TARGET TERMINATION RECEIVED BY PI7C8148A ...........................................................32
2.8.4 TARGET TERMINATION INITIATED BY PI7C8148A...........................................................34
3 ADDRESS DECODING..............................................................................................................................36
3.1 ADDRESS RANGES ............................................................................................................................36
3.2 I/O ADDRESS DECODING..................................................................................................................36
3.2.1 I/O BASE AND LIMIT ADDRESS REGISTER .........................................................................37
3.2.2 ISA MODE ....................................................................................................................................37
3.3 MEMORY ADDRESS DECODING .....................................................................................................38
3.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ..................................38
3.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ..........................39
Page 5 of 90
JUNE 2004 – Revision 1.04
5 Page 
PI7C8148A
2-PORT PCI-TO-PCI BRIDGE
ADVANCE IwNwFwO.RDaMtaASTheIOetN4U.com
INTRODUCTION
Product Description
The PI7C8148A is Pericom Semiconductor’s PCI-to-PCI Bridge, designed to be fully compliant with
the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8148A
supports synchronous bus transactions between devices on the Primary Bus and the Secondary Buses
operating up to 66MHz. Both primary and secondary buses must operate at the same frequency. The
primary and secondary buses can also operate in concurrent mode, resulting in added increase in system
performance.
Product Features
! 32-bit Primary and Secondary Ports run up to 66MHz
! Compliant with the PCI Local Bus Specification, Revision 2.2
! Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
- All I/O and memory commands
- Type 1 to Type 0 configuration conversion
- Type 1 to Type 1 configuration forwarding
- Type 1 configuration write to special cycle conversion
! Compliant with the Advanced Configuration Power Interface (ACPI)
! Compliant with the PCI Power Management Specification, Revision 1.1
! Compliant with the PCI Mobile Design Guide, Revision 1.1
! Provides internal arbitration for four secondary bus masters
- Programmable 2-level priority arbiter
! Supports serial EEPROM interface for register auto-load and VPD access
! Supports posted write buffers in all directions
! Dynamic Prefetching Control
! Four 128 byte FIFO’s for delay transactions
! Two 128 byte FIFO’s for posted memory transactions
! Enhanced address decoding
! 32-bit I/O address range
! 32-bit memory-mapped I/O address range
! 64-bit prefetchable address range
! Extended commercial temperature range 0°C to 85°C
! 3.3V and 5V signaling
! 160-pin LFBGA package
Page 11 of 90
JUNE 2004 – Revision 1.04
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PI7C8148A.PDF ] | |
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