PDF PI6C5930 Data sheet ( Hoja de datos )

Número de pieza	PI6C5930
Descripción	Low Skew CMOS PLL Clock Driver
Fabricantes	Pericom Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de PI6C5930 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas
No Preview Available ! www.DataSheet4U.com PI6C5930 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 Low Skew CMOS PLL Clock Driver Features • Wide frequency range: 100 MHz max. • Five Q and one Q/2 outputs • Output skew < 250ps (rising edges) • Internal RC loop filter network • Low noise TTL-compatible outputs • Balanced drive outputs: +24mA • Outputs Hi-Z and registers reset when OE = LOW • PLL bypass for testing and low-frequency applications • Small footprint 20-pin QSOP package (Q) Description The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs. An internal loop filter eliminates the need for external compensation. This driver generates six clock outputs: Q0 through Q4 running at the same frequency, plus Q/2 which runs at one half the frequency of Q0-Q4. Thanks to design improvements, the PI6C5930 is capable of generating highly stable frequencies up to 100 MHz, while main- taining less than 250 ps skew between outputs. When FREQ_SEL = HIGH, applying either one of the Q0-Q4 outputs to the FEEDBACK pin results in five copies of the reference input. If Q/2 is applied to the FEEDBACK pin, five clocks at double the reference input are created. The output enable (OE) function may be used to turn all outputs off and save power. The FREQ_SEL input is set to LOW if the SYNC frequency is lower than 30 MHz, otherwise it should be set HIGH. The PLL_EN function can be used for testing and to bypass the PLL in low frequency applications. Block Diagram SYNC OE FEEDBACK PHASE DETECTOR LOOP FILTER VCO PLL_EN FREQ_SEL 01 1 ÷2 0 RD Q RD Q RD Q RD Q RD Q RD QQ Pin Configuration GND OE FEEDBACK AVCC VCC GND SYNC FREQ_SEL GND Q0 1 20 2 19 3 18 4 17 5 20-Pin Q 16 6 15 7 14 8 13 9 12 10 11 Q4 Q/2 GND Q3 VCC Q2 GND PLL_EN GND Q1 Q/2 Q4 Q3 Q2 Q1 Q0 1 PS7084D 08/10/99 1 page PI6C5930 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567L89o0w121S23k45e6w789C012M34O5w6w7S8w9P0.1DL2a3L4ta56SC7h8e9leo01tc42k1U2.3cD4o5rm67iv89e0r12 Test Loads OUTPUT 30pF 300Ω 300Ω 7.0V OUTPUT VCC 160Ω 68Ω 20pF Used for output enable/disable parameters. Ordering Information P/N Max. Output Freq. Pkg. PI6C5930Q 100 MHz 20-pin QSOP Used for all other timing parameters. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS7084D 08/10/99 5 Page

Páginas	Total 5 Páginas
PDF Descargar	[ Datasheet PI6C5930.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
PI6C5930	Low Skew CMOS PLL Clock Driver	Pericom Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar