PDF CS4265 Data sheet ( Hoja de datos )

Número de pieza	CS4265
Descripción	104dB 24-Bit 192kHz Stereo Audio CODEC
Fabricantes	Cirrus Logic
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CS4265 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC D/A Features  Multi-Bit Delta Sigma Modulator  104 dB Dynamic Range  -90 dB THD+N  Up to 192 kHz Sampling Rates  Single-Ended Analog Architecture  Volume Control with Soft Ramp – 0.5 dB Step Size – Zero Crossing, Click-Free Transitions  Popguard® Technology – Minimizes the Effects of Output Transients  Filtered Line-Level Outputs  Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit – Right-Justified 16-, 18-, 20-, and 24-bit  Selectable 50/15 µs De-Emphasis A/D Features  Multi-Bit Delta Sigma Modulator  104 dB Dynamic Range  -95 dB THD+N  Stereo 2:1 Input Multiplexer  Programmable Gain Amplifier (PGA) – ± 12 dB Gain, 0.5 dB Step Size – Zero Crossing, Click-Free Transitions  Pseudo-Differential Stereo Line Inputs  Stereo Microphone Inputs – +32 dB Gain Stage – Low-Noise Bias Supply  Up to 192 kHz Sampling Rates  Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit  High-Pass Filter or DC Offset Calibration 1.8 V to 5 V Serial Audio Input Serial Audio Output I2C Control Data Reset 3.3 V to 5 V 3.3 V to 5 V Volume Control Interpolation Filter Multibit Modulator Volume Control Interpolation Filter Multibit Modulator Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter Mute Control Left DAC Output Mute Control Right DAC Output IEC60958-3 Transmitter High Pass Filter Low-Latency Anti-Alias Filter High Pass Filter Low-Latency Anti-Alias Filter Internal Voltage Reference Mic Bias Multibit Oversampling ADC Multibit Oversampling ADC PGA PGA MUX +32 dB +32 dB Transmitter Output Microphone Bias Mic Input 1&2 Stereo Line Input http://www.cirrus.com Copyright  Cirrus Logic, Inc. 2012 (All Rights Reserved) AUG '12 DS657F3 1 page CS4265 11.1.1 Accessing the E Buffer ........................................................................................................ 54 11.2 Serial Copy Management System (SCMS) .................................................................................. 54 11.3 Channel Status Data E Buffer Access .......................................................................................... 54 11.3.1 One-Byte Mode ................................................................................................................... 55 11.3.2 Two-Byte Mode ................................................................................................................... 55 12. PACKAGE DIMENSIONS .................................................................................................................. 56 13. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................... 56 14. ORDERING INFORMATION ........................................................................................................ 57 15. REVISION HISTORY .......................................................................................................................... 57 LIST OF FIGURES Figure 1.DAC Output Test Load ................................................................................................................ 12 Figure 2.Maximum DAC Loading .............................................................................................................. 12 Figure 3.Master Mode Serial Audio Port Timing ....................................................................................... 20 Figure 4.Slave Mode Serial Audio Port Timing ......................................................................................... 20 Figure 5.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 21 Figure 6.Format 1, I²S up to 24-Bit Data ................................................................................................... 21 Figure 7.Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 21 Figure 8.Control Port Timing - I²C Format ................................................................................................. 22 Figure 9.Typical Connection Diagram ....................................................................................................... 23 Figure 10.Master Mode Clocking .............................................................................................................. 25 Figure 11.Analog Input Architecture .......................................................................................................... 27 Figure 12.Pseudo-Differential Input Stage ................................................................................................ 28 Figure 13.De-Emphasis Curve .................................................................................................................. 29 Figure 14.Suggested Active-Low Mute Circuit .......................................................................................... 30 Figure 15.Control Port Timing, I²C Write ................................................................................................... 32 Figure 16.Control Port Timing, I²C Read ................................................................................................... 32 Figure 17.De-Emphasis Curve .................................................................................................................. 38 Figure 18.DAC Single-Speed Stopband Rejection ................................................................................... 48 Figure 19.DAC Single-Speed Transition Band .......................................................................................... 48 Figure 20.DAC Single-Speed Transition Band .......................................................................................... 48 Figure 21.DAC Single-Speed Passband Ripple ........................................................................................ 48 Figure 22.DAC Double-Speed Stopband Rejection .................................................................................. 48 Figure 23.DAC Double-Speed Transition Band ........................................................................................ 48 Figure 24.DAC Double-Speed Transition Band ........................................................................................ 49 Figure 25.DAC Double-Speed Passband Ripple ...................................................................................... 49 Figure 26.DAC Quad-Speed Stopband Rejection ..................................................................................... 49 Figure 27.DAC Quad-Speed Transition Band ........................................................................................... 49 Figure 28.DAC Quad-Speed Transition Band ........................................................................................... 49 Figure 29.DAC Quad-Speed Passband Ripple ......................................................................................... 49 Figure 30.ADC Single-Speed Stopband Rejection ................................................................................... 50 Figure 31.ADC Single-Speed Stopband Rejection ................................................................................... 50 Figure 32.ADC Single-Speed Transition Band (Detail) ............................................................................. 50 Figure 33.ADC Single-Speed Passband Ripple ........................................................................................ 50 Figure 34.ADC Double-Speed Stopband Rejection .................................................................................. 50 Figure 35.ADC Double-Speed Stopband Rejection .................................................................................. 50 Figure 36.ADC Double-Speed Transition Band (Detail) ............................................................................ 51 Figure 37.ADC Double-Speed Passband Ripple ...................................................................................... 51 Figure 38.ADC Quad-Speed Stopband Rejection ..................................................................................... 51 Figure 39.ADC Quad-Speed Stopband Rejection ..................................................................................... 51 Figure 40.ADC Quad-Speed Transition Band (Detail) .............................................................................. 51 Figure 41.ADC Quad-Speed Passband Ripple ......................................................................................... 51 DS657F3 5 5 Page CS4265 6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp’s stability. CL affects the dominant pole of the internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable. DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 7,10) Combined Digital and On-chip Analog Filter Response Symbol Min Typ Max Single-Speed Mode Unit Passband (Note 7) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 8) Group Delay De-emphasis Error (Note 9) Fs = 44.1 kHz Combined Digital and On-chip Analog Filter Response tgd 0 - 0.35 0 - 0.4992 -0.175 - +0.01 0.5465 - - 50 - - - 10/Fs - - - +0.05/-0.25 Double-Speed Mode Fs Fs dB Fs dB s dB Passband (Note 7) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 8) Group Delay Combined Digital and On-chip Analog Filter Response tgd 0- 0- -0.15 - 0.5770 - 55 - - 5/Fs Quad-Speed Mode 0.22 0.501 +0.15 - - - Fs Fs dB Fs dB s Passband (Note 7) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay to -0.1 dB corner to -3 dB corner (Note 8) tgd 0 0 -0.12 0.7 51 - - - - - - 2.5/Fs 0.110 0.469 0 - - - Fs Fs dB Fs dB s 7. Filter response is guaranteed by design. 8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 9. De-emphasis is available only in Single-Speed Mode. 10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. DS657F3 11 11 Page

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