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PDF CYNSE10526 Data sheet ( Hoja de datos )
| Número de pieza | CYNSE10526 | |
| Descripción | Ayama 10000 Network Search Engine | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CONFIDENTIAL
PRELIMINARY
CYNSE10512
wwCw.YDaNtaSShEee1t40U.2co5m6
CYNSE10128
Ayama™ 10000
Network Search Engine
Cypress Semiconductor Corporation
Document #: 38-02069 Rev. *F
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised July 13, 2004
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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
wwCwY.DaNtaSShEee1t40U1.c2om8
LIST OF FIGURES
Figure 2-1. Ayama™ 10000 Block Diagram .......................................................................................... 11
Figure 2-2. Example of Switch/Router Implementation Using Ayama 10000 ........................................ 12
Figure 3-1. Ayama 10000 Database Table Widths ................................................................................ 13
Figure 3-2. Multi-Width Database Configuration Example..................................................................... 13
Figure 3-3. Addressing the Ayama 10000 Data and Mask Arrays......................................................... 14
Figure 5-1. Blocks and Block Registers Association ............................................................................. 19
Figure 5-2. Mini-Key Register Contents................................................................................................. 19
Figure 5-3. Sub-Blocks and Soft Priority Associations .......................................................................... 20
Figure 5-4. Timing Diagram of a DQ Bus Parity Error (288-bit Search, TLSZ=00)................................ 21
Figure 5-5. Timing Diagram of a Core Parity Error (TLSZ=00).............................................................. 22
Figure 5-6. MultiSearch Operation Overview......................................................................................... 22
Figure 5-7. Ayama 10000 I/O Interfaces................................................................................................ 24
Figure 5-8. Comparand Register Selection During Search and Learn Instructions ............................... 26
Figure 5-9. Addressing the Global Mask Register Array ....................................................................... 27
Figure 5-10. Search Successful Register .............................................................................................. 27
Figure 5-11. Command Register ........................................................................................................... 28
Figure 5-12. Information Register .......................................................................................................... 30
Figure 5-13. Read Burst Register .......................................................................................................... 30
Figure 5-14. Write Burst Address Register ............................................................................................ 31
Figure 5-15. Next-free Address Register ............................................................................................... 31
Figure 5-16. Configuration Register....................................................................................................... 32
Figure 5-17. Hardware Register ............................................................................................................ 33
Figure 5-18. Parity Control Register ...................................................................................................... 34
Figure 5-19. Selection of the CPR through GMR Index......................................................................... 35
Figure 5-20. Control Register ................................................................................................................ 35
Figure 5-21. Search Result Register ..................................................................................................... 36
Figure 5-22. Block Mini-Key Register .................................................................................................... 37
Figure 5-23. Block Priority Register ....................................................................................................... 38
Figure 5-24. Block Parity Register ......................................................................................................... 39
Figure 5-25. Block NFA Register ........................................................................................................... 39
Figure 5-26. Block Priority Register Aliases .......................................................................................... 40
Figure 5-27. Ayama 10000 Clocks (CLK2X and PHS_L) ...................................................................... 42
Figure 5-28. Ayama 10000 Clocks (CLK1X).......................................................................................... 42
Figure 5-29. Ayama 10000 Clocks for All Timing Diagrams .................................................................. 42
Figure 5-30. Data Array, Mask Array and External SRAM Address Space Encoding ........................... 44
Figure 5-31. Internal Register Address Space Encoding....................................................................... 45
Figure 5-32. Depth Cascading in a Single Block ................................................................................... 46
Figure 5-33. Depth Cascading 4 Blocks ................................................................................................ 47
Figure 5-34. FULL Signal Generation in a Cascaded Table.................................................................. 48
Figure 5-35. Proper Power-up Sequence .............................................................................................. 49
Figure 6-1. Single-Location Read Cycle Timing .................................................................................... 52
Figure 6-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ......................................................... 53
Figure 6-3. Single Write Cycle Timing ................................................................................................... 54
Figure 6-4. Burst Write of the Data and Mask Arrays (BLEN = 4) ......................................................... 55
Figure 6-5. Timing Diagram for Mixed Single Search (One Device)...................................................... 57
Figure 6-6. Multiwidth Configurations Using CYNSE10512 as an Example .......................................... 58
Figure 6-7. Timing Diagram for Mixed MultiSearch (One Device) ......................................................... 59
Figure 6-8. Multiwidth Configurations Using CYNSE10512 as an Example .......................................... 60
Figure 6-9. Hardware Diagram for a Table with Eight Devices.............................................................. 61
Document #: 38-02069 Rev. *F
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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
wwCwY.DaNtaSShEee1t40U1.c2om8
2.0 Overview
Cypress Semiconductor Corporation’s (Cypress’s) Ayama™ 10000 Network Search Engine (NSE) is designed to be a high-
performance, pipelined, synchronous, 512K/256K/128K 36-bit entries NSE. This high-speed, high-capacity Ayama 10000 NSE
can be deployed in a variety of networking and communications applications. It can be used to accelerate network protocols such
as Longest-Prefix Match (CIDR), ARP, MPLS, and other layer 2, 3, and 4 protocols. The performance and features of the
Ayama 10000 make it attractive in applications such as Enterprise LAN switches and routers, and broadband switching and/or
routing equipment that supports multiple data rates at OC–48 and beyond. Ayama 10000 can operate at a maximum performance
of 266 million searches per second (MSPS).
The Ayama 10000 is designed to be scalable in order to support network database sizes of up to 15872K 36-bit entries specifically
for environments that require large network policy databases. It includes features that ease table management, reduce power
consumption and improve data integrity. The device can have its features individually enabled or disabled for flexibility based on
the needs of the applications. The Ayama 10000’s Data and Mask arrays that make up the Core are organized into blocks that
can be individually configured to optimize the device performance and provide even more flexibility.
Figure 2-1 below shows the block diagram of the Ayama 10000.
CLK_MODE
PHS_L
CLK1X/CLK2X
RST_L
CMD[10:0]
CMDV
ACK
EOT
ID[4:0]
Command
Decode
and
PIO Access
Control and Configuration
Internal Registers
TAP
Controller
TMS
TCK
TRST_L
TDI
TDO
DQ[71:0]
PAR[1:0]
PARERR_L
Parity
CMD Compare / PIO Data
Block Associated
Internal Registers
Data Array
Mask Array
Pipeline
and
SRAM
Interface
Control
SADR[N:0],
OE_L
WE_L
CE_L
ALE_L
N = 25 for
CYNSE10512,
24 for
CYNSE10256,
23 for
CYNSE10128
MULTI_HIT
FULL
FULI[6:0]/LHI_1[6:0]
LHI[6:0]/LHI_0[6:0]
BHI[2:0]
Full Logic
Arbitration
Logic
Figure 2-1. Ayama™ 10000 Block Diagram
FULO[1:0]/LHO_1[1:0]
LHO[1:0]/LHO_0[1:0]
BHO[2:0]
SSF
SSV
Document #: 38-02069 Rev. *F
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