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PDF CY25200 Data sheet ( Hoja de datos )
| Número de pieza | CY25200 | |
| Descripción | Programmable Spread Spectrum Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
■ Wide operating output (SSCLK) frequency range
❐ 3–200 MHz
■ Programmable spread spectrum with nominal 31.5 kHz
modulation frequency
■ Center spread: ±0.25% to ±2.5%
■ Down spread: –0.5% to –5.0%
■ Input frequency range
❐ External crystal: 8–30 MHz fundamental crystals
❐ External reference: 8–166 MHz clock
■ Integrated phase-locked loop (PLL)
■ Programmable crystal load capacitor tuning array
■ Low cycle-to-cycle jitter
■ 3.3V operation with 2.5V output clock drive option
■ Spread spectrum On and Off function
■ Power down or Output Enable function
■ Output frequency select option
■ Field-programmable
■ Package: 16 pin TSSOP
Benefits
■ Suitable for most PC peripherals, networking, and consumer
applications.
■ Provides wide range of spread percentages for maximum EMI
reduction to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development and
manufacturing costs and time to market.
■ Eliminates the need for expensive and difficult to use higher
order crystals.
■ Internal PLL generates up to 200 MHz outputs; also generates
custom frequencies from an external crystal or a driven source.
■ Enables fine tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
■ Application compatibility in standard and low power systems.
■ Provides ability to enable or disable spread spectrum with an
external pin.
■ Enables low power state or output clocks to High-Z state.
■ Enables quick generation of sample prototype quantities.
Logic Block Diagram
XIN/CLKIN 1
XOUT 16
CXOUT
OSC.
CXIN
QΦ
VCO
P
PLL
Divider
Bank 1
Divider
Bank 2
Output
Select
Matrix
2
VDD
3 5 13 11 6
AVDD AVSS VSS VDDL VSSL
4 10
CP0 CP1
7 SSCLK1
8 SSCLK2
9 SSCLK3
12 SSCLK4
14 SSCLK5/REFOUT/CP2
15 SSCLK6/REFOUT/CP3
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07633 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 11, 2007
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Table 4. Using Clock Select, CLKSEL Control Pin
Input Frequency
(MHz)
14.318
CLKSEL
(Pin 4)
CLKSEL = 0
SSCLK1
(Pin 7)
33.33
CLKSEL = 1
66.66
SSCLK2
(Pin 8)
33.33
66.66
SSCLK3
(Pin 9)
33.33
66.66
SSCLK4
(Pin 12)
33.33
66.66
REFOUT
(Pin 14)
14.318
14.318
Figure 3. Using Clock Select, CLKSEL Control Pin Configuration Pinout
14.318MHz
VDD
AVDD
CLKSEL
AVSS
VSSL
33.33/66.66MHz
33.33/66.66MHz
1
2
3
4
5
6
7
8
16 XOUT
15 REFOUT(14.318MHz)
14 REFOUT(14.318MHz)
13 VSS
12 33.33/66.66MHz
11 VDDL
10 SSON
9 33.33/66.66MHz
REFOUT
(Pin 15)
14.318
14.318
Document #: 38-07633 Rev. *D
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Ordering Information
Ordering Code[6]
Package Type
Programming Temperature Operating Range
CY25200ZXC_XXXW 16-lead TSSOP (Pb Free)
Factory Commercial, 0 to 70°C
CY25200ZXC_XXXWT 16-lead TSSOP – Tape and Reel (Pb Free)
Factory Commercial, 0 to 70°C
CY25200FZXC
16-lead TSSOP (Pb Free)
Field
Commercial, 0 to 70°C
CY25200FZXCT
16-lead TSSOP – Tape and Reel (Pb Free)
Field
Commercial, 0 to 70°C
CY3672
FTG Development Kit
N/A N/A
CY3672-PRG
FTG Programmer
N/A N/A
CY3695
CY22050F/CY22150F/CY25200F Socket Adapter
N/A N/A
Table 5. 16-lead TSSOP Package Characteristics
Parameter
θJA
Name
theta JA
Package Drawing and Dimensions
Value
115
Figure 8. 16-lead TSSOP 4.40 MM Body Z16.173
Unit
°C/W
PIN 1 ID
1
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
DIMENSIONS IN MM[INCHES] MIN.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
MAX.
0.65[0.025]
BSC.
0.85[0.033]
0.95[0.037]
16
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
0.076[0.003]
SEATING
PLANE
0.25[0.010]
BSC
GAUGE
PLANE
0° -8°
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Notes
5. Skew and phase alignment is guaranteed within all SSCLK outputs and within both REFOUT outputs. SSCLK and REFOUT outputs are not phase aligned to each other.
6. “XXX” denotes the assigned product dash number. “W” denotes the different revisions of the product.
Document #: 38-07633 Rev. *D
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