PDF CY28439-2 Data sheet ( Hoja de datos )

Número de pieza	CY28439-2
Descripción	Clock Generator
Fabricantes	Cypress Semiconductor
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PRELIMINARY www.DataSheet4U.com CY28439-2 Clock Generator for Intel Grantsdale Chipset Features • Compliant to Intel CK410 • Supports Intel Prescott and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks (two selectable between Fixed and Overclocking) • 96-MHz differential dot clock • 48-MHz USB clocks • 33-MHz PCI clock • Dial-A-Frequency Block Diagram Xin Xout FS_[E:A] 14.318MHz Crystal PLL Reference PLL1 CPU Divider VTTPWR_GD#/PD PLL2 SRC Divider PLL3 SATA Divider PLL4 Fixed Divider SDATA SCLK I2C Logic Watchdog Timer VDD_RE F RE F IREF VDD_CPU CPUT CPUC VDD_SRC SRCT (PCI Ex) SRCC (PCI Ex) VDD_SRC SRCT4_SATA SRCC4_SATA VDD_48Mhz DOT96T DOT96C VDD_48 USB48 VDD_48 24/48 VDD_PCI PCI VDD_PCI PCIF SRESET# • Watchdog • Two independent overclocking PLLs • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU SRC PCI REF DOT96 USB x2 x6 x9 x2 x1 x1 24-48M x1 Pin Configuration VSS_PCI PCI3 FS_E/PCI4 PCI5 VSS_PCI VDD_PCI PCIF0 FS_A/PCIF1 FS_B/PCIF2 VDD_48 SEL24_48#/24_48M USB48 VSS_48 DOT96T DOT96C VTTPWRGD#/PD SRCT0 SRCC0 VDD_SRC VSS_SRC SRCT1 SRCC1 SRCT2 SRCC2 VSS_SRC SRCT_SATAT SRCC_SATAC VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 VDD_PCI 55 PCI2 54 PCI1 53 PCI0 52 SRESET# 51 REF1/FS_D 50 REF0/FS_C** 49 VSS_REF 48 XIN 47 XOUT 46 VDD_REF 45 SCLK 44 SDATA 43 CPUT0 42 CPUC0 41 VDD_CPU 40 CPUT1 39 CPUC1 38 VSS_CPU 37 IREF 36 VSSA 35 VDDA 34 VDD_SRC 33 SRCT4 32 SRCC4 31 SRCT3 30 SRCC3 29 VSS_SRC * Indicates internal pull-up ** Indicates internal pull-down Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07750 Rev. B Revised July 07, 2005 1 page Control Registers Byte 0: Control Register 0 Bit @Pup 71 61 51 41 31 21 11 01 Byte 1: Control Register 1 Bit @Pup 71 61 51 41 30 21 11 01 Byte 2: Control Register 2 Bit @Pup 71 61 51 41 31 21 11 PRELIMINARY Name RESERVED SRC[T/C]4 SRC[T/C]3 SATA[T/C] SRC[T/C]2 SRC[T/C]1 RESERVED SRC[T/C]0 Description RESERVED SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SATA[T/C] Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable RESERVED SRC[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable Name PCIF0 DOT_96[T/C] 24_48M REF0 RESERVED CPU[T/C]1 CPU[T/C]0 CPU Description PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled 24_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled RESERVED CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Name PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 PCIF2 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled PCIF2 Output Enable 0 = Disabled, 1 = Enabled Description www.CDaYta2Sh8ee4t43U9.c-o2m Document #: 38-07750 Rev. B Page 5 of 22 5 Page PRELIMINARY www.CDaYta2Sh8ee4t43U9.c-o2m Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci1 Ci2 Pin 3 to 6p X1 Cs1 X2 Cs2 XTAL Trace 2.8pF Ce1 Ce2 Trim 33pF Figure 3. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 ( Ce1 + 1 Cs1 + Ci1 + Ce2 + 1 Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) Dial-A-Frequency (CPU and SRC) This feature allows the user to overclock their system by slowly stepping up the CPU or SRC frequency. When the program- mable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Figure 1 for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in Figure 1. In this mode, the user writes the desired N and M value into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value if required. Associated Register Bits CPU_DAF Enable—This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note: the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF). CPU_DAF_N—There will be nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000) The allowable values for N are detailed in the frequency select table in Figure 1. CPU DAF M—There will be 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, the allowable values for M are detailed in the frequency select table in Figure 1. SRC_DAF Enable—This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note: the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF). SRC_DAF_N—There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000) The allowable values for N are detailed in the frequency select table in Figure 1. Recovery—The recovery mechanism during CPU DAF when the system locks up and the Watchdog timer is enabled is determined by the “Watchdog Recovery Mode” and “Watchdog Autorecovery Enable” bits. The possible recovery methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW, and (D) No recovery, just send reset signal. There is no recovery mode for SRC Dial-a-Frequency. Software Frequency Select This mode allows the user to select the CPU output frequencies using the Software Frequency select bits in the SMBUS register. FSEL—There will be four bits (for 16 combinations) to select predetermined CPU frequencies from a table. The table selec- tions are detailed in section Figure 1. Document #: 38-07750 Rev. *B Page 11 of 22 11 Page

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