PDF CY7C1511AV18 Data sheet ( Hoja de datos )

Número de pieza	CY7C1511AV18
Descripción	72-Mbit QDR-II SRAM 4-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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CY7C1511AV18, CwYww7.DCat1a5Sh2ee6t4AU.Vco1m8 CY7C1513AV18, CY7C1515AV18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled ■ Operates as a QDR-I device with 1 cycle read latency in DLL off mode ■ Available in x 8, x 9, x 18, and x 36 configurations ■ Full data coherency, providing most current data ■ Core VDD = 1.8 (± 0.1V); IO VDDQ = 1.4V to VDD ■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ Variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1511AV18 – 8M x 8 CY7C1526AV18 – 8M x 9 CY7C1513AV18 – 4M x 18 CY7C1515AV18 – 2M x 36 Functional Description The CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II archi- tecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1511AV18), 9-bit words (CY7C1526AV18), 18-bit words (CY7C1513AV18), or 36-bit words (CY7C1515AV18) that burst sequentially into or out of the device. Because data can be trans- ferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 300 x8 930 x9 940 x18 1020 x36 1230 278 MHz 278 865 870 950 1140 250 MHz 250 790 795 865 1040 200 MHz 200 655 660 715 850 167 MHz 167 570 575 615 725 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-06985 Rev. C • San Jose, CA 95134-1709 • 408-943-2600 Revised September 27, 2007 [+] Feedback 1 page CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CwwYw7.DCat1aS5he1e5t4AU.cVo1m8 Pin Configuration (continued) The pin configuration for CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1513AV18 (4M x 18) 123456789 A CQ NC/144M A WPS BWS1 K NC/288M RPS A B NC Q9 D9 A NC K BWS0 A NC C NC NC D10 VSS A NC A VSS NC D NC D11 Q10 VSS VSS VSS VSS VSS NC E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC M NC NC D16 VSS VSS VSS VSS VSS NC N NC D17 Q16 VSS A A A VSS NC P NC NC Q17 A A C A A NC R TDO TCK A A A C A A A 10 A NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI CY7C1515AV18 (2M x 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/288M A WPS BWS2 K BWS1 RPS A NC/144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A C A A A TMS TDI Document Number: 001-06985 Rev. C Page 5 of 31 [+] Feedback 5 Page CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CwwYw7.DCat1aS5he1e5t4AU.cVo1m8 Write Cycle Descriptions The write cycle description table for CY7C1511AV18 and CY7C1513AV18 follows. [2, 10] BWS0/ BWS1/ K NWS0 NWS1 K Comments L L L–H – During the data portion of a write sequence : CY7C1511AV18 − both nibbles (D[7:0]) are written into the device, CY7C1513AV18 − both bytes (D[17:0]) are written into the device. L L – L-H During the data portion of a write sequence : CY7C1511AV18 − both nibbles (D[7:0]) are written into the device, CY7C1513AV18 − both bytes (D[17:0]) are written into the device. L H L–H – During the data portion of a write sequence : CY7C1511AV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1513AV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L H – L–H During the data portion of a write sequence : CY7C1511AV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1513AV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. H L L–H – During the data portion of a write sequence : CY7C1511AV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1513AV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. H L – L–H During the data portion of a write sequence : CY7C1511AV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1513AV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1526AV18 follows. [2, 10] BWS0 L L H K L–H – L–H K – During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device. L–H During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device. – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Note 10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-06985 Rev. *C Page 11 of 31 [+] Feedback 11 Page

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