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PDF EBE10AE8ACFA Data sheet ( Hoja de datos )
| Número de pieza | EBE10AE8ACFA | |
| Descripción | 1GB Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
1GB Registered DDR2 SDRAM DIMM
EBE10AE8ACFA (128M words × 72 bits, 1 Rank)
Specifications
• Density: 1GB
• Organization
128M words × 72 bits, 1 rank
• Mounting 9 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 1 piece of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1074E30 (Ver. 3.0)
Date Published July 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008
1 page  
EBE10AE8ACFA
Serial PD Matrix
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Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 0 60H
1
Module data width
0 1 0 0 1 0 0 0 48H
72
Module data width continuation
0 0 0 0 0 0 0 0 00H
0
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-8E
0 0 1 0 0 1 0 1 25H
-6E 0 0 1 1 0 0 0 0 30H
SDRAM access from clock (tAC)
-8E
0 1 0 0 0 0 0 0 40H
-6E 0 1 0 0 0 1 0 1 45H
DIMM configuration type
0 0 0 0 0 1 1 0 06H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
SSTL 1.8V
2.5ns*1
3.0ns*1
0.4ns*1
0.45ns*1
ECC, Address/
Command Parity
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
0
4,8
8
3, 4, 5
4.00mm max.
DIMM type information
0 0 0 0 0 0 0 1 01H
Registered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH
Normal
Weak Driver
50Ω ODT
Support
3.75ns*1
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
Minimum row precharge time (tRP)
-8E
0
0
1
1
0
0
1
0
32H
-6E 0 0 1 1 1 1 0 0 3CH
0.5ns*1
5.0ns*1
0.6ns*1
12.5ns
15ns
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH
Minimum /RAS to /CAS delay (tRCD)
-8E
0
0
1
1
0
0
1
0
32H
7.5ns
12.5ns
-6E
Minimum active to precharge time
(tRAS)
0 0 1 1 1 1 0 0 3CH
0 0 1 0 1 1 0 1 2DH
15ns
45ns
Data Sheet E1074E30 (Ver. 3.0)
5
5 Page 
EBE10AE8ACFA
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
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Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
DDR2-800
DDR2-667
Maximum undershoot area below VSS
DDR2-800
DDR2-667
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
Maximum undershoot area below VSS
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDDQ
Maximum undershoot area below VSSQ
Pins
Command, Address,
CKE, ODT
CK, /CK
DQ, DQS, /DQS,
UDQS, /UDQS,
LDQS, /LDQS,
RDQS, /RDQS,
DM, UDM, LDM
Specification
0.5
0.5
0.66
0.8
0.66
0.8
0.5
0.5
0.23
0.23
0.5
0.5
0.23
0.23
Unit
V
V
V-ns
V-ns
V-ns
V-ns
V
V
V-ns
V-ns
V
V
V-ns
V-ns
Volts (V) VDD, VDDQ
VSS, VSSQ
Maximum amplitude
Overshoot area
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Data Sheet E1074E30 (Ver. 3.0)
11
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