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PDF CY7C1463AV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1463AV33 | |
| Descripción | Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1461AV33
CY7C1463AV33, CwwYw7.DCat1aS4he6e5t4AU.cVo3m3
36 Mbit (1M x 36/2 M x 18/512K x 72)
Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
■ 3.3V and 2.5V IO power supply
■ Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self timed writes
■ Asynchronous Output Enable
■ CY7C1461AV33, CY7C1463AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 165-Ball FBGA package. CY7C1465AV33
available in Pb-free and non-Pb-free 209-Ball FBGA package
■ Three chip enables for simple depth expansion
■ Automatic power down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability — linear or interleaved burst order
■ Low standby power
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Functional Description
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-Through
Burst SRAMs designed specifically to support unlimited true
back-to-back read and write operations without the insertion of
wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is
equipped with the advanced NoBL logic required to enable
consecutive read and write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in systems
that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
133 MHz
6.5
310
120
100 MHz
8.5
290
120
Unit
ns
mA
mA
Note
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05356 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 05, 2008
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Pin Configurations (continued)
CY7C1461AV33
CY7C1463AV33, wCwYw.7DCata1Sh4e6et54UA.cVom33
100-Pin TQFP Pinout
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1463AV33
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68
DQA
BYTE A
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05356 Rev. *G
Page 5 of 32
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CY7C1461AV33
CY7C1463AV33, wCwYw.7DCata1Sh4e6et54UA.cVom33
Truth Table
The truth table for CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 follows. [2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE1
CE2
CE3
ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect Cycle
None H X X L L X X X L L->H Tri-State
Deselect Cycle
None X X H L L X X X L L->H Tri-State
Deselect Cycle
None X L X L L X X X L L->H Tri-State
Continue Deselect Cycle
None X X X L H X X X L L->H Tri-State
Read Cycle (Begin Burst)
External L H L L L H X L L L->H Data Out
(Q)
Read Cycle (Continue Burst)
Next
XXXL
H
X X L L L->H Data Out
(Q)
NOP/Dummy Read
(Begin Burst)
External L H L L L H X H L L->H Tri-State
Dummy Read (Continue Burst)
Next
XXXL
H
X X H L L->H Tri-State
Write Cycle (Begin Burst)
External L H L L L L L X L L->H Data In (D)
Write Cycle (Continue Burst)
Next
XXXL
H
X L X L L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
LHL L
L
L H X L L->H Tri-State
Write Abort (Continue Burst)
Next
XXXL
H
X H X L L->H Tri-State
Ignore Clock Edge (Stall)
Current X X X L
X
X X X H L->H
–
Sleep Mode
None X X X H X X X X X X Tri-State
Notes
2. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for read or write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05356 Rev. *G
Page 11 of 32
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