PDF CY7C1463AV25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1463AV25
Descripción	Flow-Through SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C1461AV25 CwwYw7.DCat1a4Sh6ee3t4AU.Vco2m5 CY7C1465AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description[1] • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin-compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V/1.8V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • CY7C1461AV25, CY7C1463AV25 available in JEDEC-standard lead-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package. CY7C1465AV25 available in lead-free and non-lead-free 209-ball FBGA package. • Three chip enables for simple depth expansion • Automatic Power-down feature available using ZZ mode or CE deselect • IEEE 1149.1 JTAG-Compatible Boundary Scan • Burst Capability—linear or interleaved burst order • Low standby power The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are 2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV25/CY7C1463AV25/ CY7C1465AV25 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 6.5 270 120 100 MHz 8.5 250 120 Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Unit ns mA mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05355 Rev. E Revised June 22, 2006 1 page Pin Configurations (continued) 100-pin TQFP Pinout BYTE B NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1463AV25 CY7C1461AV25 CY7C1463AV25 CwYw7w.CDa1ta4Sh6e5etA4UV.c2om5 80 A 79 NC 78 NC 77 VDDQ 76 VSS 75 NC 74 DQPA 73 DQA 72 DQA 71 VSS 70 VDDQ 69 DQA 68 DQA 67 66 VSS NC BYTE A 65 VDD 64 ZZ 63 DQA 62 DQA 61 VDDQ 60 VSS 59 DQA 58 DQA 57 NC 56 NC 55 VSS 54 VDDQ 53 NC 52 NC 51 NC Document #: 38-05355 Rev. E Page 5 of 29 5 Page CY7C1461AV25 CY7C1463AV25 CwYw7w.CDa1ta4Sh6e5etA4UV.c2om5 Truth Table for Read/Write[2, 3, 9] Function (CY7C1461AV25) Read Write No bytes written Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Byte C – (DQC and DQPC) Write Byte D – (DQD and DQPD) Write All Bytes Truth Table for Read/Write[2, 3, 9] WE BWA BWB BWC BWD HXXXX L HHHH L LHHH L H L HH L HH L H L HHH L LLLLL Function (CY7C1463AV25) Read Write – No Bytes Written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Both Bytes Truth Table for Read/Write[2, 3, 9] Read Function (CY7C1465AV25) Write – No Bytes Written Write Byte X − (DQx and DQPx) Write All Bytes WE BWB HX LH LH LL LL WE H L L L BWA X H L H L BWX X H L All BW = L Note: 9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05355 Rev. *E Page 11 of 29 11 Page

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