|
|
PDF MAX2991 Data sheet ( Hoja de datos )
| Número de pieza | MAX2991 | |
| Descripción | Power-Line Communications (PLC) Integrated Analog Front-End Transceiver | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX2991 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
19-5125; Rev 0; 1/10
www.DataSheet4U.com
Power-Line Communications (PLC) Integrated
Analog Front-End Transceiver
General Description
The MAX2991 power-line communication analog front-
end (AFE) is a state-of-the-art integrated circuit that
delivers high integration and superb performance, while
reducing the total system cost. The MAX2991 is the first
AFE specifically designed for OFDM (orthogonal fre-
quency division multiplexing) modulated signal transmis-
sion over power lines. Operating in the 10kHz to 490kHz
band, the programmable filters allow compliance with
CENELEC, FCC, and ARIB standards using the same
device.
The MAX2991 transceiver provides two main paths:
transmit (Tx) path and receive (Rx) path. The transmit
path injects an OFDM modulated signal into the AC or
DC line. The transmit path is composed of a digital IIR
filter, digital-to-analog converter (DAC), followed by a
lowpass filter, and a preline driver. The receiver path is
for the signal enhancement, filtering, and digitization of
the received signal. The receiver is composed of a low-
pass and a highpass filter, a two-stage automatic gain
control (AGC), and an analog-to-digital converter (ADC).
The integrated AGC maximizes the dynamic range of the
signal up to 60dB, while the lowpass filter removes any
out-of-band noise, and selects the desired frequency
band. The ADC converts the enhanced and amplified
input signal to a digital format. An integrated offset can-
cellation loop minimizes the DC offset.
The MAX2991, along with the MAX2990 PLC baseband
modem, delivers the most cost-effective data communi-
cation solution over power-line networks in the market.
The MAX2991 is specified over the -40NC to +85NC
temperature range and is available in a 48-pin LQFP
package.
Features
S Optimized to Operate with the MAX2990 PLC
Baseband
S Integrated Band Select Filter, AGC, and 10-Bit
ADC for Rx Path
S Integrated Wave-Shaping Filter, Programmable
Predriver Gain, and 10-Bit DAC for Tx Path
S Variable Sampling Rate Up to 1.2Msps
S Built-In 60dB Dynamic Range AGC and DC Offset
Cancellation
S Programmable Filters Operate in the CENELEC,
FCC, and ARIB Frequency Bands
S Single 3.3V Power Supply
S 70mA Typical Supply Current (Half-Duplex Mode)
S Extended Operating Temperature Range
Applications
Automatic Meter Reading
Home Automation
Heating Ventilation and Air Conditioning (HVAC)
Building Automation
Industrial Automation
Lighting Control
Sensor Control and Data Acquisition (SCADA)
Remote Monitoring and Control
Security Systems/Keyless Entry
Smart Grid
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX2991ECM+ -40NC to +85NC
48 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Application Circuit
HOST
APPLICATION
µC
MAX2990
MCU
INTERFACE
PHY
MAX2991
Tx BLOCK
AFE
Rx BLOCK
LINE
DRIVER
LINE
COUPLER
AC POWER
LINE
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
Power-Line Communications (PLC) Integrated
Analog Front-End Transceiver
SPI™ TIMING CHARACTERISTICS (Figure 2)
PARAMETER
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to SCLK Setup
CS Low After SCLK Hold
CS High to SCLK Setup
CS High After SCLK Hold
CS Pulse-Width High
SDIN to SCLK Setup
SDIN Hold After SCLK
SDOUT Valid Before SCLK
SDOUT Valid After SCLK
SYMBOL
fCLK
tCP
tCH
tCL
tCSS0
tCSH0
tCSS1
tCSH1
tCSW
tDS
tDH
tDO1
tDO2
CONDITIONS
MIN TYP MAX UNITS
20 MHz
50 ns
20 ns
20 ns
10 ns
10 ns
10 ns
10 ns
20 ns
10 ns
10 ns
20 ns
5 ns
CS
SCLK
tCSH0
tCSS0
SDIN
tDS
tDO1
SDOUT
Figure 2. SPI Interface Timing Diagram
tCH tCL
tDH
tDO2
tCSW
tCP
tCSH1
tCSS1
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDIN X A6 A5 A4 A3 A2 A1 A0 R/W D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
Figure 3. SPI Communication Protocol
SPI is a trademark of Motorola, Inc.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
Power-Line Communications (PLC) Integrated
Analog Front-End Transceiver
Detailed Description
The MAX2991 power-line AFE integrated circuit is a
state-of-the-art CMOS device that delivers high perfor-
mance and low cost. This highly integrated design com-
bines an ADC, DAC, signal conditioning, and predriver
as shown in the Functional Diagram. The MAX2991
meets all frequency band requirements of the various
popular power-line standards such as FCC, ARIB, and
CENELEC.
The MAX2991 along with the MAX2990 PLC baseband
modem deliver the most cost-effective data communi-
cation solution over power-line networks in the market.
The advanced design of the MAX2991 allows operation
without external controls, enabling simplified connection
to a variety of third-party power-line digital PHY devices.
The MAX2991 includes various control signals to achieve
additional power reduction.
Receive Channel
The receiver channel consists of a low-noise variable-
gain amplifier (VGA1) followed by a lowpass filter (LPF),
a highpass filter (HPF), and another variable-gain ampli-
fier (VGA2) circuit. An ADC samples the VGA2 output.
An AFE interface provides data communication to the
digital PHY device.
The variable-gain low-noise amplifier reduces the receiv-
er channel input-referred noise by providing additional
signal gain to the AFE input. The filter blocks remove
any out-of-band noise, provide anti-aliasing, and select a
proper AFE bandwidth. Using the adaptation blocks, the
VGAs scale the received signal to maintain the optimum
signal level at the ADC input.
The 10-bit ADC samples the analog signal and converts
it to a 10-bit digital stream with a maximum 1.2Msps
sampling rate.
Transmit Channel
The transmit channel consists of a 10-bit DAC, an image-
reject lowpass filter, and a programmable-gain predriv-
er. The DAC receives the data stream from the digital
PHY device through the AFE interface. The 10-bit DAC
provides a complementary function to the receive chan-
nel with a maximum 1.2Msps sampling rate. The DAC
converts the 10-bit digital stream to an analog voltage.
The lowpass filter removes spurs and harmonics adja-
cent to the desired passband to reduce any out-of-band
transmitted frequencies and energy from the DAC out-
put. The lowpass filter ensures that the transmitted signal
meets bandwidth requirements specified by the different
wideband and narrowband standards.
The predriver controls the output level of the lowpass
filter connected to an external line driver, which, in turn,
connects to the power-line medium. The output level is
adjustable by the predriver gain control that provides up
to 6dB gain and 10dB attenuation.
Serial Interface
The MAX2991 features two separate serial interfaces:
host SPI interface and AFE interface. The host SPI inter-
face provides direct access to the MAX2991 configura-
tion registers, while the AFE interface allows data com-
munication with the PLC baseband modem (MAX2990)
and also provides indirect access to the MAX2991 con-
figuration registers.
Host SPI Interface
The MAX2991 host SPI interface provides access to
the configuration registers using CS, SCLK, SDIN, and
SDOUT. A host SPI frame consists of a 7-bit register
address, a read/write bit, and 16 bits of data. Data is
driven on the rising edge of SCLK and sampled on the
falling edge of SCLK. Figure 3 shows a valid host SPI
communication protocol.
AFE Interface
The AFE interface allows the MAX2991 to communicate
with the PLC baseband modem (MAX2990) through
a transmit channel (TXCLK, TXDATA, TXCONV) and
a receive channel (RXCLK, RXDATA, RXCONV), and
provides indirect access to the MAX2991 configuration
registers. See the Interfacing to the MAX2990 Baseband
section for connection details.
AFE Interface Transmit Enable (ENTX)
ENTX enables the transmitter of the MAX2991 AFE cir-
cuit. A logic-high on ENTX powers down the MAX2991
transmitter.
AFE Interface Receiver Enable (ENRX)
ENRX enables the receiver on the MAX2991. A logic-
high on ENRX powers down the MAX2991 receiver.
AFE Interface Tx Clock (TXCLK)
The TXCLK signal provides the clock to the MAX2991
AFE transmitter. Apply a 19.2MHz clock at TXCLK to
achieve 1.2Msps data rate.
AFE Interface Rx Clock (RXCLK)
The RXCLK signal provides the clock to the MAX2991
AFE receiver. Apply a 19.2MHz clock at RXCLK to
achieve 1.2Msps data rate.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX2991.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX2990 | 10kHz to 490kHz OFDM-Based Power Line Communication Modem | Maxim Integrated Products |
| MAX2991 | Power-Line Communications (PLC) Integrated Analog Front-End Transceiver | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |