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PDF TLE8203E Data sheet ( Hoja de datos )
| Número de pieza | TLE8203E | |
| Descripción | Mirror Power IC | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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Final Data Sheet, Rev. 1.0, February 2009
TLE 8203E
Mirror Power IC
www.DataSheet4U.com
Automotive Power
1 page  
3 Pin Configuration
3.1 Pin Assignment
TLE 8203E
Pin Configuration
*1'
287
287
96
,1+
3:0
3:0
,62
9''
'2
&/.
&61
',
*2
QF
QF
QF
*1'
*1'
QF
287
96
287
287
96
287
QF
&3
96
287
QF
QF
QF
QF
QF
*1'
www.DFaitgaSuhreeet24U.comPin Configuration PG-DSO-36-50
3.2 Pin Definitions and Functions
Pin
cooling
tab
1, 18,
19, 36
2
3
4, 26,
30, 33
5
Symbol
GND
GND
OUT5
OUT6
VS
INH
6 PWM1
7 PWM2
Function
Cooling Tab; internally connected to GND;
To reduce thermal resistance, place cooling areas and thermal vias on PCB.
Ground; internally connected to cooling tab (exposed pad).
Power-Output of Half-Bridge output 5; DMOS half-bridge (mirror position).
Power-Output of Half-Bridge output 6; DMOS half-bridge (mirror position).
Power Supply; needs decoupling capacitors to GND. > 47 µF electrolytic in parallel
with 100 nF ceramic is recommended. All VS pins must be connected externally.
Inhibit; active low. Sets the device in sleep mode with low current consumption
when left open or pulled to LOW. Has an internal pull-down current source.
Logic Input for Direct Power Stage Control; direct input to control the high-side
switches selected by the SPI xsel1 bits in control register CtrlReg01.
Logic Input for Direct Power Stage Control; direct input to control the switches
selected by the SPI xsel2 bits in control register CtrlReg11.
Final Data Sheet
5 Rev. 1.0, 2009-02-04
5 Page 
TLE 8203E
Power Supply
6 Power Supply
6.1 General
The TLE 8203E has two power domains: All power drivers are connected to the supply voltage VS which is
connected to the automotive 12 V board-net. The internal logic part is supplied by a separate Voltage VDD = 5 V.
The advantage of this system is that information stored in the logic remains intact in the event of short-term failures
in the supply voltage VS. The system can therefore continue to operate after VS has recovered, without having to
be reprogrammed.
A rising edge on VDD triggers an internal Power-On Reset (POR) to initialize the IC at power-on. All data stored
internally is deleted, and the outputs are switched to high-impedance status (tristate).
6.2 Sleep-Mode
The TLE 8203E can be put in a low current-consumption mode by setting the input INH to LOW. The INH pin has
an internal pull-down current source. In sleep-mode, all output transistors are turned off and the SPI is not
operating. When enabling the IC by setting INH from L to H, a Power-On Reset is performed as described above.
6.3 Reverse Polarity
The TLE 8203E requires an external reverse polarity protection. The gate-driver (charge-pump output) for an
external n-channel logic-level MOSFET is integrated. The gate voltage is provided at pin GO which should be
connected as shown in the application diagram.
6.4 Electrical Characteristics
Electrical Characteristics: Power Supply
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter
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Symbol
Limit Values
Min. Typ. Max.
Unit
Conditions
Current Consumption
6.4.1 Supply current
IS – 1.0 7.0 mA –
6.4.2 Logic supply current
IDD
–
2.5 10
mA SPI not active
6.4.3
6.4.4
6.4.5
Supply quiescent current
Logic quiescent current
Total quiescent current
IS_Q
–
IDD_Q
–
IS_Q + IDD_Q –
2.5 5
0.2 1
36
µA INH = L;
µA VS = 14 V;
µA
VOUTX = 0 V;
Tj < 85 °C
Charge Pump-output for Reverse-Polarity Protection FET (GO)
6.4.6
6.4.7
6.4.8
Gate-Voltage
Setup-time
Reverse leakage current
VGO - VS
5
–
8
V IGO = 50 µA
tGO – – 1 ms –
IlkGO
– – 5 µA VS = 0 V;
VGO = -14 V
Final Data Sheet
11 Rev. 1.0, 2009-02-04
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet TLE8203E.PDF ] | |
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