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PDF NB7V585M Data sheet ( Hoja de datos )
| Número de pieza | NB7V585M | |
| Descripción | 1.8 V / 2.5 V Differential 2:1 Mux Input To 1:6 CML Clock/Data Fanout Buffer/Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB7V585M
1.8V / 2.5V Differential 2:1
Mux Input to 1:6 CML
Clock/Data Fanout
Buffer/Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB7V585M is a differential 1−to−6 CML clock/data
distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50 W
termination resistors and will accept LVPECL, CML, or LVDS logic
levels (see Figure 9). The NB7V585M produces six identical output
copies of clock or data operating up to 6 GHz or 10 Gb/s, respectively.
As such, NB7V585M is ideal for SONET, GigE, Fiber Channel,
Backplane and other clock/data distribution applications. The 16 mA
differential CML output structure provides matching internal 50 W
source terminations, 400 mV output swings when externally
terminated with a 50 W resistor to VCC (see Figure 14) and is
optimized for low skew and minimal jitter. The NB7V585M is
powered with either 1.8 V or 2.5 V supply and is offered in a low
profile 5x5 mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7V585M is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz
• Random Clock Jitter < 0.8 ps RMS, Max
www.Dat•aSLheoewt4US.kceowm 1:6 CML Outputs, 20 ps Max
• 2:1 Multi−Level Mux Inputs
• 175 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential CML Outputs, 330 mV Peak−to−Peak, Typical
• Operating Range: VCC = 1.71 V to 1.89 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM*
1 32
1
QFN32
MN SUFFIX
CASE 488AM
NB7V
585M
AWLYYWW
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED LOGIC DIAGRAM
VCC
Q0
Q0
Q1
SEL Q1
VREFAC0
IN0
VT0
IN0
0
Q2
Q2
IN1
VT1
IN1
VREFAC1
VCC
GND
Q3
1 Q3
Q4
Q4
Q5
Q5
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
NB7V585M/D
1 page  
NB7V585M
Table 6. AC CHARACTERISTICS VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min Typ Max
Unit
fMAX
Maximum Input Clock Frequency, VOUTPP w 200 mV
6.0 7.0
fDATAMAX Maximum Operating Input Data Rate (PRBS23)
10
VOUTPP Output Voltage Amplitude (See Figures 4, Note 15)
fin v 4.0 GHz
250
400
fin v 6.0 GHz 200 325
GHz
Gbps
mV
tPLH, tPHL Propagation Delay to Output Differential @ 1 GHz, INx/INx to Qn/Qn 125 175 250 ps
Measured at Differential Crosspoint
SEL to Qn
200 300
tPLH TC
tSKEW
Propagation Delay Temperature Coefficient
Output − Output Skew (Within Device) (Note 12)
Device − Device Skew (tpd Max − tpdmin)
100 fs/°C
30 ps
50
tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 4.0 GHz 45 50 55 %
tJITTER
Output Random Jitter (RJ) (Note 13)
Deterministic Jitter (DJ) (Note 14)
fin v 6.0 GHz
fin v 10 Gbps
0.2 0.8 ps rms
10 ps pk−pk
VINPP
tr, tf
Input Voltage Swing (Differential Configuration) (Note 15)
Output Rise/Fall Times @ 1 GHz (20% − 80%)
Qn, Qn
100
1200
mV
50 65 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
450
400
VCC
350
300
www.DataSheet4U.com
250
200
150 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typical)
INx
50 W
VTx
50 W
INx
Figure 3. Input Structure
http://onsemi.com
5
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