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PDF NB7VPQ16M Data sheet ( Hoja de datos )

Número de pieza NB7VPQ16M
Descripción 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver
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No Preview Available ! NB7VPQ16M Hoja de datos, Descripción, Manual

NB7VPQ16M
1.8V/2.5V CML 12.5 Gbps
Programmable Pre-Emphasis
Copper/Cable Driver with
Selectable Equalizer Receiver
MultiLevel Inputs w/ Internal Termination
Description
The NB7VPQ16M is a high performance single channel
programmable PreEmphasis CML Driver with a selectable Equalizer
Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V
power supply. When placed in series with a Data/Clock path, the
NB7VPQ16M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect. Therefore, the
serial data rate is increased by reducing InterSymbol Interference
(ISI) caused by losses in copper interconnect or long cables.
The PreEmphasis buffer is controlled using a serial bus via the
Serial Data In (SDIN) and Serial Clock In (SCLKIN) control inputs
and contains circuitry which provides sixteen programmable
PreEmphasis settings to select the optimal output compensation
level.
These selectable output levels will handle various backplane lengths
and cable lines. The first four SDIN bits (D3:D0) will digitally select
0 dB through 12 dB typical of deemphasis (see Table 1).
For cascaded applications, the shifted SDIN and SCLKIN signals
are presented at the SDOUT and SCLKOUT pins.
The 5thbit (LSB) of the serial data bits allows for enabling the
equalization function of the receiver.
The differential Data / Clock inputs incorporate a pair of internal
www.Dat5a0ShWeette4rUm.cionmation resistors, in a 100 W centertapped configuration,
via the VT pin and will accept LVPECL, CML or LVDS logic levels.
This feature provides transmission line termination onchip, at the
receiver end, eliminating external components.
The NB7VPQ16M is a member of the GigaCommFamily of high
performance Data/Clock products with PreEmphasis/Equalization
(PEEQ).
http://onsemi.com
MARKING
DIAGRAM*
16
1
1
QFN16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB7V
PQ16M
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
IN
VT
IN
SDIN
SCLKIN
SLOAD
EQ
SDI
DAC
PE
SDOUT
SCLKOUT
Q
Q
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Features
Maximum Input Data Rate > 12.5 Gbps
Maximum Input Clock Frequency > 8 GHz
Drives Up To 18inches of FR4
(16) Programmable Output Deemphasis Levels; 0 dB
through 12 dB
200 ps Typical Propagation Delay
Differential CML Outputs, 400 mV PeaktoPeak,
Typical (PE = 0 dB)
Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V
Internal Output Termination Resistors, 50 W
QFN16 Package, 3 mm x 3 mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
© Semiconductor Components Industries, LLC, 2009
July, 2009 Rev. 0
1
Publication Order Number:
NB7VPQ16M/D

1 page




NB7VPQ16M pdf
NB7VPQ16M
Table 4. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Internal Input Pulldown Resistor
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Value
> 4 kV
> 200 V
75 kW
Level 1
UL 94 V0 @ 0.125 in
416
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1 Condition 2
Rating
Unit
VCC, VCCD Positive Power Supply
VIN Positive Input Voltage
GND = 0 V
GND = 0 V
3.0
0.5 to VCC
+0.5
V
V
VINPP
Iout
Differential Input Voltage |IN IN|
Output Current
Continuous
Surge
1.89 V
34 mA
40
IIN Input Current Through RT (50 W Resistor)
$40
mA
TA Operating Temperature Range
40 to +85
°C
Tstg Storage Temperature Range
65 to +150
°C
qJA
Thermal Resistance (JunctiontoAmbient) (Note 4) TGSD
516 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 lfpm
500 lfpm
QFN16
QFN16
42 °C/W
35
qJC Thermal Resistance (JunctiontoCase)
Standard Board QFN16
4 °C/W
Tsol Wave Solder
PbFree
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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http://onsemi.com
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NB7VPQ16M arduino
NB7VPQ16M
DUTA
INA
DUTB
INB
DUTC
INC
SLOAD
Serial Data In SDINA
Serial Clock In
SCLKINA
EQA
PEA
CML
SDOUTA SLOAD
SDINB
SCLKINB
SCLKOUTA
EQB
PEB
CML
SDOUTB SLOAD
SDINC
SCLKINC
SCLKOUTB
QA QB
Figure 13. Simplified Cascaded Logic Diagram
EQC
PEC
CML
SDOUTC
SCLKOUTC
QC
SDIN
DUTC
DUTB
DUTA
D3C D2C D1C D0C EQC D3B D2B D1B D0B EQB D3A D2A D1A D0A EQA
SCLKIN 1
23
45
67
8 9 10 11 12 13 14 15
SDOUT
5 Clocks
SCLKIN to SDOUT
tPD
5 Clocks
DUTC
XXXXXXXXXXXXXXXXX D3C D2C D1C D0C EQC
5 Clocks
DUTB
D3B D2B D1B D0B EQB
DUTA
D3A D2A D1A
D0A EQA
SCLKOUT
1 23 4
tPD
SCLKIN to SCLKOUT
5
67
8 9 10 11 12 13 14 15 16 17 18 19
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
www.DataSheeStL4OUA.Dcom
tPWMin
tS3
IN
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
IN
Figure 14. Simplified Cascaded Serial Data/Clock Timing Diagram
http://onsemi.com
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