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PDF LTC2265-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2265-12 | |
| Descripción | (LTC226x-12) 65Msps Low Power Dual ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2265-12 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LTC2265-12/
LTC2264-12/LTC2263-12
12-Bit, 65Msps/40Msps/
25Msps Low Power Dual ADCs
FEATURES
n 2-Channel Simultaneous Sampling ADC
n 71dB SNR
n 90dB SFDR
n Low Power: 167mW/112mW/94mW Total
n 83mW/56mW/47mW per Channel
n Single 1.8V Supply
n Serial LVDS Outputs: 1 or 2 Bits per Channel
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full Power Bandwidth S/H
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit and 12-Bit Versions
n 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multichannel Data Acquisition
n Nondestructive Testing
wwwL.Da, LtaT,SLThCe, LeTtM4,UL.inceoamr Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
DESCRIPTION
The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel,
simultaneous sampling 12-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSBRMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
TYPICAL APPLICATION
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
+
S/H
–
+
S/H
–
1.8V
VDD
12-BIT
ADC CORE
12-BIT
ADC CORE
PLL
GND
1.8V
OVDD
DATA
SERIALIZER
OUT1A
OUT1B
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
OGND
226512 TA01
SERIALIZED
LVDS
OUTPUTS
LTC2265-12, 65Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20
FREQUENCY (MHz)
30
226512 TA02
22654312f
1
1 page  
LTC2265-12/
LTC2264-12/LTC2263-12
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
Differential Encode Mode (ENC– Not Tied to GND)
VID Differential Input Voltage
VICM Common Mode Input Voltage
VIN Input Voltage Range
RIN Input Resistance
(Note 8)
Internally Set
Externally Set (Note 8)
ENC+, ENC– to GND
(See Figure 10)
l 0.2
V
1.2
l 1.1
1.6
V
V
l 0.2
3.6 V
10 kΩ
CIN Input Capacitance
Single-Ended Encode Mode (ENC– Tied to GND)
3.5 pF
VIH High Level Input Voltage
VIL Low Level Input Voltage
VIN Input Voltage Range
RIN Input Resistance
VDD = 1.8V
VDD = 1.8V
ENC+ to GND
(See Figure 11)
l 1.2
V
l 0.6 V
l0
3.6 V
30 kΩ
CIN Input Capacitance
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
3.5
pF
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Input Current
CIN Input Capacitance
VDD = 1.8V
VDD = 1.8V
VIN = 0V to 3.6V
l 1.3
V
l 0.6 V
l –10
10 μA
3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND
IOH Logic High Output Leakage Current
COUT Output Capacitance
DIGITAL DATA OUTPUTS
VDD = 1.8V, SDO = 0V
SDO = 0V to 3.6V
200 Ω
l –10
10 μA
3 pF
wwwV.DODataSheeDt4ifUfe.rceonmtial Output Voltage
100Ω Differential Load, 3.5mA Mode
l 247
350
454 mV
100Ω Differential Load, 1.75mA Mode
l 125
175
250 mV
VOS Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l 1.125
l 1.125
1.250
1.250
1.375
1.375
V
V
RTERM On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100 Ω
22654312f
5
5 Page 
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2265-12: Integral
Nonlinearity (INL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226512 G01
LTC2265-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226512 G02
LTC2265-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
www.Da–ta12S0heet4U.com
0 10 20 30
FREQUENCY (MHz)
226512 G04
LTC2265-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20
FREQUENCY (MHz)
30
226512 G07
LTC2265-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20
FREQUENCY (MHz)
30
226512 G05
LTC2265-12: Shorted Input
Histogram
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
2049
2050
2051
2052
OUTPUT CODE
2053
226512 G08
LTC2265-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20
FREQUENCY (MHz)
30
226512 G03
LTC2265-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20
FREQUENCY (MHz)
30
226512 G06
LTC2265-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
72
71
70
69
68
67
66
0 50 100 150 200 250 300 350
INPUT FREQUENCY (MHz)
226512 G09
22654312f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2265-12.PDF ] | |
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