PDF ICS8516I Data sheet ( Hoja de datos )

Número de pieza	ICS8516I
Descripción	1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS8516I LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP GENERAL DESCRIPTION The ICS8516I is a low skew, high performance ICS 1-to-16 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8516I CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516I provides a low power, low noise, point-to-point solution for distributing clock signals over controlled impedances of 100Ω. Dual output enable inputs allow the ICS8516I to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the ICS8516I ideal for those applications demanding well defined performance and repeatability. FEATURES • 16 Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLK input • Multiple output enable inputs for disabling unused outputs in reduced fanout applications • LVDS compatible • Output skew: 65ps (maximum) • Part-to-part skew: 550ps (maximum) • Propagation delay: 2.4ns (maximum) • 3.3V operating supply • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM www.DataShCeLeKt4U.com nCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 OE1 OE2 8516FYI PIN ASSIGNMENT Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8 VDD nQ5 Q5 nQ4 Q4 VDD GND nQ3 Q3 nQ2 Q2 VDD 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 ICS8516I 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 VDD nQ10 Q10 nQ11 Q11 VDD GND nQ12 Q12 nQ13 Q13 VDD 48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View www.icst.com/products/hiperclocks.html 1 REV. A JULY 30, 2004 1 page Integrated Circuit Systems, Inc. ICS8516I LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VOD ∆ VOD VOS ∆ VOS IOZ IOFF IOSD IOS/IOSB Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Short Circuit Current Output Short Circuit Current Minimum 250 1.125 -10 -1 Typical 400 1.4 Maximum 600 50 1.6 50 +10 +1 -5.5 -12 Units mV mV V mV µA µA mA mA TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum fMAX tPD tsk(o) Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 700 1.6 2.0 2.4 65 tsk(pp) Part-to-Part Skew; NOTE 3, 4 550 tR/tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% ƒ≤ 600MHz 50 45 600 55 tPZL, tPZH Output Enable Time; NOTE 5 tPLZ, tPHZ Output Disable Time; NOTE 5 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. www.DatNaSOhTeEet34U: D.ceofmined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. 5 5 Units MHz ns ps ps ps % ns ns 8516FYI www.icst.com/products/hiperclocks.html 5 REV. A JULY 30, 2004 5 Page Integrated Circuit Systems, Inc. ICS8516I LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP www.DataSheet4U.com 8516FYI TABLE 7. PACKAGE DIMENSIONS SYMBOL JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBC MINIMUM NOMINAL N 48 A -- -- A1 0.05 -- A2 1.35 1.40 b 0.17 0.22 c 0.09 -- D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 θ 0° -- ccc -- -- Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.html 11 MAXIMUM 1.60 0.15 1.45 0.27 0.20 0.75 7° 0.08 REV. A JULY 30, 2004 11 Page

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