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PDF CY7C1370B Data sheet ( Hoja de datos )
| Número de pieza | CY7C1370B | |
| Descripción | (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1370B
CY7C1372B
512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200, 167, 150, and 133 MHz
• Fast access time: 3.0, 3.4, 3.8, and 4.2 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +10% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Single WE (Read/Write) control pin
• Positive clock-edge triggered address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte Write (BWSa–BWSd) control (may be
tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan (BGA package only)
• Available in 119-ball bump BGA and 100-pin TQFP
packages
• Automatic power down available using ZZ mode or CE
deselect
Functional Description
The CY7C1370B and CY7C1372B SRAMs are designed to
eliminate dead cycles when transitions from Read to Write or
vice versa. These SRAMs are optimized for 100 percent bus
utilization and achieve Zero Bus Latency. They integrate
524,288 × 36 and 1,048,576 × 18 SRAM cells, respectively,
with advanced synchronous peripheral circuitry and a 2-bit
counter for internal burst operation. The Synchronous Burst
SRAM family employs high-speed, low-power CMOS designs
www.DautsaiSngheeatd4Uva.cnocmed single-layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2, and CE3), cycle start input (ADV/LD),
Clock enable (CEN), byte Write Enables (BWSa, BWSb,
BWSc, and BWSd), and Read-Write Control (WE). BWSc and
BWSd apply to CY7C1370B only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A Clock enable (CEN) pin allows operation of the
CY7C1370B/CY7C1372B to be suspended as long as
necessary. All synchronous inputs are ignored when CEN is
HIGH and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE3) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(Read or Write) will be completed. The data bus will be in
high-impedance state two cycles after the chip is deselected
or a Write cycle is initiated.
The CY7C1370B and CY7C1372B have an on-chip two-bit
burst counter. In the burst mode, the CY7C1370B and
CY7C1372B provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is
defined by the MODE input pin. The MODE pin selects
between linear and interleaved burst sequence. The ADV/LD
signal is used to load a new external address (ADV/LD = LOW)
or increment the internal burst counter (ADV/LD = HIGH)
Output enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Logic Block Diagram
CLK
CE
DaDta-In
Q
REG.
ADV/LD
Ax
CY7C1370 CY7C1372
AX X = 18:0
X = 19:0
DQX X = a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
CEN
CE1
CE2
CE3
WE
BWSX
Mode
OE
CONTROL
and Write
LOGIC
256K × 36/
512K × 18
MEMORY
ARRAY
DQX
DPX
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05197 Rev. **
Revised December 3, 2001
1 page  
CY7C1370B
CY7C1372B
Pin Definitions
Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK Input-Clock
CE1 Input-
Synchronous
CE2 Input-
Synchronous
CE3 Input-
Synchronous
OE Input-
Asynchronous
CEN
Input-
Synchronous
DQa
DQb
www.DaDtaQShceet4U.com
DQd
I/O-
Synchronous
DPa
DPb
DPc
DPd
ZZ
MODE
I/O-
Synchronous
Input-
Asynchronous
Input Pin
VDD
VDDQ
TDO
Power Supply
I/O Power
Supply
JTAG serial
output
Synchronous
Description
Address inputs used to select one of the 524,288/1,048576 address locations.
Sampled at the rising edge of the CLK.
Byte Write Select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb
and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a Write sequence.
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Output enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a Write sequence, during the first clock
when emerging from a deselected state and when the device has been deselected.
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when
required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by AX during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state
condition. The outputs are automatically three-stated during the data portion of a Write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.DQ a, b, c and d are eight-bits wide.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].
During Write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is
controlled by BWSc, and DPd is controlled by BWSd.DP a, b, c and d are one-bit wide
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA
only).
Document #: 38-05197 Rev. **
Page 5 of 27
5 Page 
CY7C1370B
CY7C1372B
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the I/O ring when these instruc-
tions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant with the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
www.DaStAaSMhPeLetE4/UP.cRoEmLOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05197 Rev. **
Page 11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CY7C1370B.PDF ] | |
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