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PDF CY7C1378C Data sheet ( Hoja de datos )
| Número de pieza | CY7C1378C | |
| Descripción | 9-Mbit (256K x 32) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1378C
9-Mbit (256K x 32) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description[1]
• Pin-compatible and functionally equivalent to ZBT®
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 256K x 32 common I/O architecture
• Single 3.3V power supply (VDD)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable (OE)
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
The CY7C1378C is a 3.3V, 256K x 32 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1378C is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.8 ns (250-MHz device)
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1378C (256K x 32)
A0, A1, A
MODE
CLK
C
CEN
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ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05687 Rev. *F
Revised September 14, 2006
1 page  
CY7C1378C
Burst Write Accesses
The CY7C1378C has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:D] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00 01 10
01 00 11
10 11 00
11 10 01
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
Fourth
Address
A1, A0
11
00
01
10
Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Address
Used
None
CE ZZ ADV/LD WE BWx OE CEN CLK
H L L X X X L L-H
DQ
Tri-State
Continue
Deselect Cycle
None X L H X X X L L-H Tri-State
Read Cycle
(Begin Burst)
External
LL
L
H X L L L-H Data Out (Q)
Read Cycle
(Continue Burst)
Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read
www.Da(taBSehgeinet4BUu.rcsotm)
External L L L H X H L L-H Tri-State
Dummy Read
(Continue Burst)
Next X L H X X H L L-H Tri-State
Write Cycle
(Begin Burst)
External L L L L L X L L-H Data In (D)
Write Cycle
(Continue Burst)
Next X L H X L X L L-H Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
LL
L
L H X L L-H Tri-State
WRITE ABORT
(Continue Burst)
Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE
Current
XL
X
X X X H L-H
(Stall)
-
SLEEP MODE
None
XH
X
X X X X X Tri-State
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies
that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table.
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05687 Rev. *F
Page 5 of 13
5 Page 
Switching Waveforms (continued)
NOP, STALL, and Deselect Cycle[17, 18, 20]
123
4
5
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
ADDRESS
A1
A2
A3 A4
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
D(A1) Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
67
Q(A3)
STALL
NOP
CY7C1378C
8 9 10
A5
D(A4)
tCHZ
Q(A5)
READ
Q(A5)
DESELECT CONTINUE
DESELECT
ZZ Mode Timing[21, 22]
DON’T CARE
UNDEFINED
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ZZ
I SUPPLY
ALL INPUTS
(except ZZ)
t ZZ
t ZZI
I DDZZ
t ZZREC
t RZZI
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
20. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
21. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device.
22. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05687 Rev. *F
Page 11 of 13
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| PDF Descargar | [ Datasheet CY7C1378C.PDF ] | |
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