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PDF ISL70001SRH Data sheet ( Hoja de datos )
| Número de pieza | ISL70001SRH | |
| Descripción | Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator | |
| Fabricantes | Intersil Corporation | |
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Radiation Hardened and SEE Hardened 6A
Synchronous Buck Regulator with Integrated
MOSFETs
ISL70001SRH
The ISL70001SRH is a radiation hardened and SEE
hardened high efficiency monolithic synchronous buck
regulator with integrated MOSFETs. This single chip
power solution operates over an input voltage range
of 3V to 5.5V and provides a tightly regulated output
voltage that is externally adjustable from 0.8V to
~85% of the input voltage. Output load current
capacity is 6A for TJ < +145°C.
The ISL70001SRH utilizes peak current-mode control
with integrated compensation and switches at a fixed
frequency of 1MHz. Two ISL70001SRH devices can be
synchronized 180° out-of-phase to reduce input RMS
ripple current. These attributes reduce the number and
size of external components required, while providing
excellent output transient response. The internal
synchronous power switches are optimized for high
efficiency and good thermal performance.
The chip features a comparator type enable input that
provides flexibility. It can be used for simple digital
on/off control or, alternately, can provide
undervoltage lockout capability by precisely sensing
the level of an external supply voltage using two
external resistors. A power-good signal indicates
when the output voltage is within ±11% typical of the
nominal output voltage.
Regulator start-up is controlled by an analog soft-start
www.ctDoiartc2auS0ih0t,emewts4hUuic.cshoinmcgananbeexatdejrunsatlecdafproamcitoarp.proximately 2ms
The ISL70001SRH incorporates fault protection for
the regulator. The protection circuits include input
undervoltage, output undervoltage and output
overcurrent.
High integration makes the ISL70001SRH an ideal
choice to power many of today’s small form factor
applications. Two devices can be synchronized to
provide a complete power solution for large scale
digital ICs, like field programmable gate arrays
(FPGAs), that require separate core and I/O voltages.
Specifications for Rad Hard QML devices are
controlled by the Defense Supply Center in
Columbus (DSCC). The SMD numbers listed in the
Ordering Information Table on page 2 must be
used when ordering.
Detailed Electrical Specifications for these
devices are contained in SMD 5962-09225. A link
is provided on our website for downloading.
Features
• Electrically Screened to DSCC SMD 5962-09225
• QML Qualified per MIL-PRF-38535 Requirements
• Full Mil-Temp Range Operation (TA = -55°C to
+125°C)
• Radiation Hardness
- Total Dose [50-300rad(Si)/s] . . . 100krad(Si) min
• SEE Hardness
- SEL and SEB LETeff . . . . . . 86.4MeV/mg/cm2 min
- SE1F.I4Xx-s1e0c-t6iocnm(2LEmTeafxf = 86.4MeV/mg/cm2)
- SE8T6.L4EMTeefVf /(m<g1/cPmul2semPinerturbation)
• High Efficiency > 90%
• Fixed 1MHz Operating Frequency
• Operates from 3V to 5.5V Supply
• ±1% Reference Voltage over Line, Load,
Temperature and Radiation
• Adjustable Output Voltage
- Two External Resistors Set VOUT from 0.8V to
~85% of VIN
• Excellent Dynamic Response
• Bi-directional SYNC Pin Allows Two Devices to be
Synchronized 180° Out-of-Phase
• Device Enable with Comparator Type Input
• Power-Good Output Voltage Monitor
• Adjustable Analog Soft-Start
• Input Undervoltage, Output Undervoltage and
Output Overcurrent Protection
• Starts Into Pre-Biased Load
Applications*(see page 16)
• FPGA, CPLD, DSP, CPU Core or I/O Voltages
• Low-Voltage, High-Density Distributed Power
Systems
December 15, 2009
FN6947.0
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL70001SRH
Typical Application Schematic
5V
100µF
VSENSE
PVIN1
1µF
PVIN2
PVIN3
PVIN4
1µF
PVIN5
PVIN6
1 DVDD
1µF
DGND
1 AVDD
1µF
AGND
www.DataSheet4U.com
EN
10nF
M/S
PORSEL
TDI
TDO
ZAP
ISL70001SRH
LX1
LX2
LX3
LX4
LX5
LX6
1µH
20V
3A
FB
0V TO 5.5V
470µF
1kΩ
1.8V
6A
4.7nF
499Ω
PGOOD
10nF
SYNC
REF
220nF
SS
100nF
FIGURE 1. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION
5 FN6947.0
December 15, 2009
5 Page 
ISL70001SRH
VREF = 0.6V
ISS = 23µA
RD = 2.2Ω
VOUT
RT
FB
PWM
LOGIC
ERROR
AMPLIFIER
-
+
+
VREF
RD
ISS
SS
REF
RB
CSS
CREF
FIGURE 6. SOFT-START CIRCUIT
Power-Good
The power-good (PGOOD) pin is an open-drain logic
output which indicates when the output voltage of the
regulator is within regulation limits. The power-good
pin pulls low during shutdown and remains low when
the controller is enabled. After a successful soft-start,
the PGOOD pin releases and the voltage rises with an
external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled
low.
The power-good circuitry monitors the FB pin and
compares it to the rising and falling thresholds shown
in the “Electrical Specifications” table on page 8. If the
feedback voltage exceeds the typical rising limit of
111% of the reference voltage, the PGOOD pin pulls
low. The PGOOD pin continues to pull low until the
www.fDeaetadSbhaecekt4Uv.oclotmage falls to a typical of 107.5% of the
reference voltage. If the feedback voltage drops below
a typical of 89% of the reference voltage, the PGOOD
pin pulls low. The PGOOD pin continues to pull low until
the feedback voltage rises to a typical 92.5% of the
reference voltage. The PGOOD pin then releases and
signals the return of the output voltage within the
power-good window.
The PGOOD pin can be pulled up to any voltage from
0V to 5.5V, independent of the supply voltage. The
pull-up resistor should have a nominal value from 1kΩ
to 10kΩ. The PGOOD pin should be bypassed to DGND
with a 10nF ceramic capacitor to mitigate SEE.
Fault Monitoring and Protection
The ISL70001SRH actively monitors output voltage
and current to detect fault conditions. Fault conditions
trigger protective measures to prevent damage to the
regulator and external load device.
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the
regulator. The feedback voltage is compared to an
undervoltage threshold that is a fixed percentage of
the reference voltage. Once the comparator trips,
indicating a valid undervoltage condition, a 3-bit
undervoltage counter increments. The counter is reset
if the feedback voltage rises back above the
undervoltage threshold plus a specified amount of
hysteresis outlined in the “Electrical Specifications”
table on page 8. If the 3-bit counter overflows, the
undervoltage protection logic shuts down the regulator.
After the regulator shuts down, it enters a delay
interval, equivalent to the soft-start interval, allowing
the device to cool. The undervoltage counter is reset
entering the delay interval. The protection logic
initiates a normal soft-start once the delay interval
ends. If the output successfully soft-starts, the power-
good signal goes high and normal operation continues.
If undervoltage conditions continue to exist during the
soft-start interval, the undervoltage counter must
overflow before the regulator shuts down again. This
hiccup mode continues indefinitely until the output
soft-starts successfully.
Overcurrent Protection
A pilot device integrated into the PMOS transistor of
Power Block 4 samples current each cycle. This current
feedback is scaled and compared to an overcurrent
threshold based on the number of Power Blocks
connected. Each additional Power Block connected
beyond Power Block 4 increases the overcurrent limit by
2A. For example, if three Power Blocks are connected,
the typical current limit threshold would be 3 x 2A = 6A.
If the sampled current exceeds the overcurrent
threshold, a 3-bit overcurrent counter increments by
one LSB. If the sampled current falls below the
threshold before the counter overflows, the counter is
reset. Once the overcurrent counter reaches 111, the
regulator shuts down.
After the regulator shuts down, it enters a delay
interval, equivalent to the soft-start interval, allowing
the device to cool. The overcurrent counter is reset
entering the delay interval. The protection logic
initiates a normal soft-start once the delay interval
ends. If the output successfully soft-starts, the power-
good signal goes high and normal operation continues.
If overcurrent conditions continue to exist during the
soft-start interval, the overcurrent counter must
overflow before the regulator shut downs the output
again. This hiccup mode continues indefinitely until the
output soft-starts successfully.
Note: It is recommended that a Schottky diode of
appropriate rating be added from the LXx pins to the
PGNDx pins to prevent severe negative ringing that
can disturb the overcurrent counter.
11 FN6947.0
December 15, 2009
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL70001SRH.PDF ] | |
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