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PDF MAX8893C Data sheet ( Hoja de datos )

Número de pieza MAX8893C
Descripción PMICs
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX8893C Hoja de datos, Descripción, Manual

19-4973; Rev 0; 10/09
EVAALVUAAILTAIOBNLEKIT
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
General Description
The MAX8893A/MAX8893B/MAX8893C power-manage-
ment integrated circuits (PMICs) are designed for a
variety of portable devices including cellular handsets.
The PMICs include a high-efficiency step-down DC-DC
converter, five low-dropout linear regulators (LDOs) with
programmable output voltages, individual power-on/
off control inputs, a load switch, and a USB high-speed
switch. These devices maintain high efficiency with a low
no-load supply current, and the small 3.0mm x 2.5mm
WLP package makes them ideal for portable devices.
The step-down DC-DC converter utilizes a proprietary
4MHz hysteretic PWM control scheme that allows for
ultra-small external components. Internal synchronous
rectification improves efficiency and eliminates the exter-
nal Schottky diode that is required in conventional step-
down converters. Its output voltage is programmable by
the I2C serial interface and output current is guaranteed
up to 500mA.
LDO1, LDO4, and LDO5 offer low 45FVRMS output noise
and low dropout of only 100mV at 100mA. They deliver
up to 300mA, 150mA, and 200mA continuous output cur-
rents, respectively. LDO2 and LDO3 each deliver 300mA
continuous output current with very low ground current.
All LDO output voltages are programmable by the I2C
serial interface. Three standard versions of the PMIC are
available with different LDO default startup voltages (see
Table 1).
www.DaTtahSeheMeAt4XU8.c8o9m3A/MAX8893B/MAX8893C are available in
a 3.0mm x 2.5mm, 30-bump WLP package.
Cellular Handsets
Smartphones and PDAs
Applications
Features
S High-Efficiency Step-Down Converter
Guaranteed 500mA Output Current
Up to 4MHz Switching Frequency
Programmable Output Voltage from 0.8V to 2.4V
Dynamic Voltage Scaling with Programmable
Ramp Rate
S Three Low-Noise LDOs with Programmable
Output Voltages
S Two Low Supply Current LDOs with
Programmable Output Voltages
S Low On-Resistance Load Switch
S USB High-Speed Switch with ±15kV ESD
S Individual Enable Control for All Regulators and
Switches
S I2C Serial Interface
S Overcurrent and Thermal Protection for All LDOs
S 3.0mm x 2.5mm x 0.64mm, 30-Bump WLP
Ordering Information
PART
MAX8893AEWV+
TEMP RANGE
-40NC to +85NC
PIN-PACKAGE
30-Bump WLP
(3.0mm x 2.5mm)
MAX8893BEWV+
-40NC to +85NC
30-Bump WLP
(3.0mm x 2.5mm)
MAX8893CEWV+
-40NC to +85NC
30-Bump WLP
(3.0mm x 2.5mm)
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX8893C pdf
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
LDO2
Input Voltage Range
CONDITIONS
Programmable Output Voltage
ILOAD = 25mA, programmable output voltage 1.2V to
3.3V in 100mV steps
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Output Voltage Accuracy
Output Current
Current Limit
Dropout Voltage
Load Regulation
Power-Supply Rejection
DVLDO2/DVBATT
Output Noise Voltage
Output Capacitor for Stable
Operation (Note 6)
Ground Current
Startup Time from Shutdown
Shutdown Output Resistance
VIN = 5.5V with ILOAD = 1mA, and
VIN = 3.0V with ILOAD = 300mA
VLDO2 = 0V
ILOAD = 200mA, TA = +25NC
1mA < ILOAD < 300mA
VENLDO2 = VBATT
10Hz to 10kHz, CLDO2 = 1FF, ILOAD = 30mA
100Hz to 100kHz, CLDO2 = 1FF, ILOAD = 30mA
0mA < ILOAD < 300mA
0mA < ILOAD < 150mA
ILOAD = 500FA
CLDO2 = 1FF, ILOAD = 300mA
LDO2_ADEN = 1, VENLDO2 = 0V
MIN TYP MAX UNIT
2.7
1.164
2.134
3.201
2.522
1.200
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.200
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.300
2.600
550
200
25
5.5
1.236
2.266
3.399
2.678
300
V
V
V
mA
mA
mV
mV
60
80
1.4 2.2
0.7 1.0
21
40
300
dB
FVRMS
FF
FA
Fs
I
_______________________________________________________________________________________   5

5 Page





MAX8893C arduino
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN TYP MAX UNIT
Maximum Pulse Width of
Spikes Suppressed
50 ns
LOAD SWITCH (LS)
Input Supply Operating Range
(VBUCK)
After VBUCK starts up
0.8 2.4 V
On-Resistance (RDS(ON))
Turn-On Delay Time (tON_DLY)
LS Rise Time (tR)
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Turn-Off Delay Time (tOFF_DLY)
LS Fall Time (tF)
Shutdown Output Resistance
VBUCK = 1.0V, ILS = 300mA, TA = +25NC
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSTOD = 0 (Note 6)
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSTOD = 1
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 0
CL = 0.1FF
CL = 1FF (Note 6)
CL = 3FF (Note 6)
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 1
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 2
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 3
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, RL = 400I, VENLS =
1.8V
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, RL = 400I, VENLS =
1.8V
CL = 0.1FF
CL = 1FF
CL = 3FF
VLS = 2.4V, VENLS = 0V, LS_ADEN = 1
50
0.85
0.85
0.85
30
34
37
10
10
10
25
27
30
100
100
100
300
300
300
11
11
11
15
150
447
100
100
200
mI
Fs
Fs
Fs
Fs
I
Note 3: VIN1, VIN2, and VBATT are connected together and single input is referred to as VIN.
Note 4: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by
design.
Note 5: When the input voltage is greater than 2.85V (typ), the UVLO comparator trips, and the threshold is reduced to 2.35V
(typ). This allows the system to start normally even if the input voltage decays to 2.35V.
Note 6: Not production tested; guaranteed by design.
Note 7: DRON(MAX) = |RON(CH1) - RON(CH2)|.
Note 8: Flatness is defined as the difference between the maximum and minimum value of on-resistance, as measured over
specified analog signal ranges.
Note 9: Between any two switches.
______________________________________________________________________________________   11

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