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PDF IS43R16320A Data sheet ( Hoja de datos )
| Número de pieza | IS43R16320A | |
| Descripción | 32Meg x 16 512-MBIT DDR SDRAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS43R16320A
ISSI®
32Meg x 16
512-MBIT DDR SDRAM
FEATURES
• Clock Frequency: 166 MHz
• Power supply (VDD and VDDQ)
DDR 333: 2.5V + 0.2V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
and Active operations
• Commands and addresses register on positive
clock edges (CK)
• Bi-directional Data Strobe signal for data cap-
ture
• Differential clock inputs (CK and CK) for
two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
with clock inputs
• Programmable burst length for Read and Write
operations
• Programmable CAS Latency (2 or 2.5 clocks)
• Programmable burst sequence: sequential or
interleaved
www.Da•taSBheuerts4Ut .ccoomncatenation and truncation supported
for maximum data throughput
• Auto Pre-charge option for each Read or Write
burst
• 8192 refresh cycles every 64ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power
Down Modes
• Lead-free package
MARCH 2006
DEVICE OVERVIEW
ISSI’s 512-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 536,870,912-bit memory
array is internally organized as four banks of 128M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
KEY TIMING PARAMETERS
Parameter
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
Clock Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
-6
DDR333
—
6
7.5
—
166
133
Unit
ns
ns
ns
MHz
MHz
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
1
1 page  
IS43R16320A
Read Command
CK
CK
CKE
CS
RAS
CAS
WE
HIGH
A0-A9
A10
BA0, BA1
CA
EN AP
DIS AP
BA
ISSI®
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
Don’t Care
www.DataSheet4U.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
5
5 Page 
IS43R16320A
ISSI®
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and
VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT
Output
(VOUT)
50Ω
Timing Reference Point
30pF
www.DataSheet4U.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/06
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IS43R16320A.PDF ] | |
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