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PDF TMP91FY28 Data sheet ( Hoja de datos )
| Número de pieza | TMP91FY28 | |
| Descripción | Original CMOS 16-Bit Microcontroller | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91FY28
www.DataSheet4U.com
Semiconductor Company
1 page  
Under development
TMP91FY28
(P60) SCK0
(P61) SO0/SDA0
(P62) SI0/SCL0
(P63) INT0
(P64) SCOUT
(P65)
(P66)
(P70) TA0IN
(P71) TA1OUT
(P72) TA3OUT
(P73)
(P74)
(P75)
(P80) TB0IN0/INT5
(P81) TB0IN1/INT6
(P82) TB0OUT0
(P83) TB0OUT1
(P84) TB1IN0/INT7
(P85) TB1IN1/INT8
(P86) TB1OUT0
(P87) TB1OUT1
(P90) SCK1
(P91) SO1/SDA1
(P92) SI1/SCL1
(P93) TXD
(P94) RXD
(P95) SCLK/ CTS
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(P96)
(PA0) INT1
(PA1) INT2
(PA2) INT3
(PA3) INT4
(PA4)
(PA5)
(PA6)
(PA7)
NMI
WAKE
DVCC [3]
DVSS [3]
I2C/SIO
(Channel 0)
8-bit timer
(TMRA0)
8-bit timer
(TMRA1)
8-bit timer
(TMRA2)
8-bit timer
(TMRA3)
16-bit timer
(TMRB0)
16-bit timer
(TMRB1)
I2C/SIO
(Channel 1)
SIO/UART
CPU (TLCS-900/L1)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
WA
BC
DE
HL
IX
IY
IZ
SP
32 bits
SR F
PC
C
High-frequency
oscillator
Clock gear
Watchdog timer
(WDT)
8-Kbyte RAM
256-Kbyte FLASH
BCD
calculator
(BCDC)
Program
patch
logic
2-Kbyte boot ROM
Interrupt
controller
Standby
controller
(KWI)
CS/WAIT
controller
10-bit
8-channel
AD
converter
( ): Initial pin function after reset
Figure 1.1 TMP91FY28 Block Diagram
91FY28-3
X1
X2
EMU0
EMU1
RESET
AM0
AM1
ALE
AD0 (P00)
AD1 (P01)
AD2 (P02)
AD3 (P03)
AD4 (P04)
AD5 (P05)
AD6 (P06)
AD7 (P07)
AD8/A8 (P10)
AD9/A9 (P11)
AD10/A10 (P12)
AD11/A11 (P13)
AD12/A12 (P14)
AD13/A13 (P15)
AD14/A14 (P16)
AD15/A15 (P17)
A0/A16 (P20)
A1/A17 (P21)
A2/A18 (P22)
A3/A19 (P23)
A4/A20 (P24)
A5/A21 (P25)
A6/A22 (P26)
A7/A23 (P27)
RD (P30)
WR (P31)
HWR (P32)
WAIT (P33)
BUSRQ (P34)
BUSAK (P35)
R/ W (P36)
BOOT (P37)
CS0 (P40)
CS1 (P41)
CS2 (P42)
CS3 (P43)
AN0/KWI0 (P50)
AN1/KWI1 (P51)
AN2/KWI2 (P52)
AN3/ ADTRG /KWI3 (P53)
AN4/KWI4 (P54)
AN5/KWI5 (P55)
AN6/KWI6 (P56)
AN7/KWI7 (P57)
AVCC
AVSS
VREFL
VREFH
2004-02-12
5 Page 
Under development
TMP91FY28
3. Functional Description
This chapter describes the flash memory of the TMP91FY28, a flash version of the TMP91CW28.
The TMP91FY28 contains a 256-Kbyte flash EEPROM and an 8-Kbyte RAM whereas the
TMP91CW28 contains an 8-Kbyte RAM and 128-Kbyte ROM. In other respects, the hardware
configuration and the functionality of the TMP91FY28 are identical to those of the TMP91CW28.
For descriptions of the configurations other than the flash memory, refer to the TMP91CW28
datasheet.
3.1 Overview of Operating Modes
The TMP91FY28 has the following two modes of operation.
The logic states on the BOOT , AM0 and AM1 after a reset determine the mode of operation
for the TMP91FY28.
Single Chip mode: The TMP91FY28 operates in Normal mode. After a reset, the TLCS-900/L1
core processor executes out of the on-chip flash memory.
Single Boot mode: After a reset, the TLCS-900/L1 core processor executes out of the on-chip boot
ROM. The boot ROM contains a routine to aid users in performing on-board
programming of the flash memory via a serial port (UART) of the TMP91FY28.
Operating Mode
Single chip mode
Single boot mode
Table 3.1.1 Modes of Operation
Input Pins
RESET
BOOT (P37)
AM0
H
H
L
AM1
H
www.DataSheet4U.com
91FY28-9
2004-02-12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMP91FY28.PDF ] | |
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