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PDF TMP91CW28 Data sheet ( Hoja de datos )
| Número de pieza | TMP91CW28 | |
| Descripción | Original CMOS 16-Bit Microcontroller | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91CW28
www.DataSheet4U.com
Semiconductor Company
1 page  
(P60) SCK0
(P61) SO0/SDA0
(P62) SI0/SCL0
(P63) INT0
(P64) SCOUT
(P65)
(P66)
(P70) TA0IN
(P71) TA1OUT
(P72) TA3OUT
(P73)
(P74)
(P75)
(P80) TB0IN0/INT5
(P81) TB0IN1/INT6
(P82) TB0OUT0
(P83) TB0OUT1
(P84) TB1IN0/INT7
(P85) TB1IN1/INT8
(P86) TB1OUT0
(P87) TB1OUT1
(P90) SCK1
(P91) SO1/SDA1
(P92) SI1/SCL1
(P93) TXD
(P94) RXD
www.Da(Pta9S5h)eSeCt4LUK./cCoTmS
(P96)
(PA0) INT1
(PA1) INT2
(PA2) INT3
(PA3) INT4
(PA4)
(PA5)
(PA6)
(PA7)
NMI
WAKE
DVCC [3]
DVSS [3]
TMP91CW28
I2C/SIO
(Channel 0)
8-bit timer
(TMRA0)
8-bit timer
(TMRA1)
8-bit timer
(TMRA2)
8-bit timer
(TMRA3)
16-bit timer
(TMRB0)
16-bit timer
(TMRB1)
I2C/SIO
(Channel 1)
SIO/UART
Interrupt
controller
CPU (TLCS-900/L1)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
WA
BC
DE
HL
IX
IY
IZ
SP
32 bits
SR F
PC
Watchdog timer
(WDT)
8-Kbyte RAM
128-Kbyte ROM
Standby
controller
(KWI)
10-bit 8-ch
AD
converter
High-frequency
oscillator
Clock gear
BCD
calculator
(BCDC)
Program
patch logic
6 banks
CS/WAIT
controller
X1
X2
EMU0
EMU1
RESET
AM0
AM1
ALE
AD0 (P00)
AD1 (P01)
AD2 (P02)
AD3 (P03)
AD4 (P04)
AD5 (P05)
AD6 (P06)
AD7 (P07)
AD8/A8 (P10)
AD9/A9 (P11)
AD10/A10 (P12)
AD11/A11 (P13)
AD12/A12 (P14)
AD13/A13 (P15)
AD14/A14 (P16)
AD15/A15 (P17)
A0/A16 (P20)
A1/A17 (P21)
A2/A18 (P22)
A3/A19 (P23)
A4/A20 (P24)
A5/A21 (P25)
A6/A22 (P26)
A7/A23 (P27)
RD (P30)
WR (P31)
HWR (P32)
WAIT (P33)
BUSRQ (P34)
BUSAK (P35)
R/ W (P36)
(P37)
CS0 (P40)
CS1 (P41)
CS2 (P42)
CS3 (P43)
AN0/KWI0 (P50)
AN1/KWI1 (P51)
AN2/KWI2 (P52)
AN3/ ADTRG /KWI3 (P53)
AN4/KWI4 (P54)
AN5/KWI5 (P55)
AN6/KWI6 (P56)
AN7/KWI7 (P57)
AVCC
AVSS
VREFL
VREFH
( ): Initial pin function after reset
Figure 1.1 TMP91CW28 Block Diagram
91CW28-3
2006-03-24
5 Page 
TMP91CW28
3. Operation
This section describes the functions and basic operation of each block constituting the
TMP91CW28.
See also section 7, “Points of Note and Restrictions” for an explanation of precautions and
restrictions for individual blocks.
3.1 CPU
The TMP91CW28 contains a high-performance 16-bit CPU called the 900/L1. For a detailed
description of the CPU, refer to “TLCS-900/L1 CPU” in the preceding chapter.
Functions unique to the TMP91CW28, which are not covered in “TLCS-900/L1 CPU”, are
described below.
3.1.1
Reset Operation
When resetting the TMP91CW28 microcontroller, ensure that the power supply voltage
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the RESET input to low level at least for 10 system clocks (32 μs at 10
MHz).
Thus, when turn on the switch, be set to the power supply voltage is within the operating
voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
RESET input to low level at least for 10 system clocks.
Clock gear is initialized 1/16 mode by reset operation. It means that the system clock
mode fSYS is set to fc/32 (= fc/16 × 1/2).
The CPU performs the following operations as a result of a reset:
• Set the program counter (PC) according to the reset vectors stored at addresses
FFFF00H to FFFF02H
PC [7:0] ← Value at FFFF00H
PC [15:8] ← Value at FFFF01H
PC [23:16] ← Value at FFFF02H
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• Set the stack pointer (XSP) to 100H.
• Set the IFF2 to IFF0 bits of the status register (SR) to 111 (Setting the interrupt
level mask register to level 7).
• Set the MAX bit of the status register (SR) to 1 (Selecting maximum mode).
• Clear the RFP2 to RFP0 bits of the status register (SR) to 000 (Selecting register
bank0).
After a reset, the CPU starts executing instructions according to the set PC. CPU
internal registers other than the above are not modified.
The on-chip I/O peripherals, ports and other pins are initialized as follows upon a reset.
• All on-chip I/O peripheral registers are initialized.
• All port pins, including those multiplexed with on-chip peripheral functions, are
configured as either general-purpose inputs or general-purpose outputs.
• The ALE pin is placed in high-impedance state.
Note: A reset operation does not affect the contents of the on-chip RAM or the CPU
registers other than PC, SR and XSP.
Figure 3.1.1 shows TMP91CW28 reset timings.
91CW28-9
2006-03-24
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMP91CW28.PDF ] | |
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